In today's rapidly changing semiconductor industry, designing high-performance and reliable analog ICs is essential. Under CMOS technology scaling, reliability (e.g., electrostatic discharge and latch-up) is degraded by device structures and stronger parasitic elements, and the analog performance is affected by short-channel effects, layout-dependent effects, and random process variations. Throughout this course, students will explore how the above factors impact the analog circuit performance and reliability, and learn both the theories and the industrial practices to address these problems.