Design and modelling of 2-D Source-Gated Transistors

Project: Research

二維源極門控晶體管的設計與建模

Status	Finished
Effective start/end date	1/01/21 → 31/12/23

Ultraflexible Monolithic Three-Dimensional Static Random Access Memory
Zhang, J., Wang, W., Zhu, J., Wang, C., Zhu, T., Zhao, C., Wang, J., Zhang, S., Wang, X., Chang, K. C., Meng, H., Chan, M. & Zhang, M., 30 Jan 2024, In: ACS Nano. 18, 4, p. 3362-3368 7 p.
Research output: Contribution to journal › Journal Article › peer-review
7 Link opens in a new tab Citations (Scopus)
Threshold Voltage Model for 2-D FETs With Undoped Body and Gated Source
Estrada, C. J., Ma, Z., Zhang, L. & Chan, M., 1 May 2023, In: IEEE Transactions on Electron Devices. 70, 5, p. 2575-2580 6 p.
Research output: Contribution to journal › Journal Article › peer-review

Open Access
5 Link opens in a new tab Citations (Scopus)
Complementary Two-Dimensional (2-D) FET Technology with MoS₂/hBN/Graphene Stack
Estrada, C. J., Ma, Z. & Chan, M., 1 Dec 2021, In: IEEE Electron Device Letters. 42, 12, p. 1890-1893 4 p.
Research output: Contribution to journal › Journal Article › peer-review

Open Access
16 Link opens in a new tab Citations (Scopus)

Project Details