Project Details
Chinese Project Title
用於高端電子系統的高速(2.4GS/s)高解析度(14比特)單通道流水線ADC芯片設計
| Status | Finished |
|---|---|
| Effective start/end date | 2/03/20 → 2/09/22 |
UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This project contributes towards the following SDG(s):
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SDG 7 Affordable and Clean Energy
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Explore the research topics touched on by this project. These labels are generated based on the underlying awards/grants. Together they form a unique fingerprint.
Research output
- 3 Journal Article
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A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration
Chen, Y., Huang, Q., Fan, Y., Zhao, Q., Huang, S. & Yuan, J., 2024, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 71, 9, p. 3961-3974 14 p.Research output: Contribution to journal › Journal Article › peer-review
6 Link opens in a new tab Citations (Scopus) -
An 8-MS/s 16-bit SAR ADC with Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process
Huang, S., Huang, Q., Fan, Y., Zhao, Q., Chen, Y., Zhang, Y. & Yuan, J., 2024, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 71, 10, p. 4486-4498 13 p.Research output: Contribution to journal › Journal Article › peer-review
1 Link opens in a new tab Citation (Scopus) -
An Injection-Locked and Sub-Sampling Clock Multiplier with a Two-Step SC DAC Achieving 2.67% Jitter Variation
Huang, Q., Huang, S., Chen, Y., Fan, Y. & Yuan, J., 2024, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 32, 10, p. 1841-1851 11 p.Research output: Contribution to journal › Journal Article › peer-review
1 Link opens in a new tab Citation (Scopus)