2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL

Ring-VCO-based PLLs are popular because of their compact chip area and wide tuning range compared with LC-VCO-based PLLs. However, they typically have higher jitter and larger frequency drift due to high sensitivity to PVT variations. Several PLL architectures were proposed to reject the phase noise and reduce the frequency drift [1,2]. However, due to an architecture-level limitation, these phase-noise-rejection PLLs inevitably degrade the settling time. To suppress large phase noise (PN) and supply sensitivity, a Type-III PLL was proposed to provide a large low-frequency loop gain by using a 3rd-order feedback loop [1]. However, high-order feedback loop degrades stability and requires low-frequency compensation zero, which needs a large loop filter and reduces the PN suppression bandwidth. To suppress the phase noise over a wide frequency offset, injection-locked (IL) PLL was proposed by injecting a clean reference into a noisy VCO [2]. But a sub-harmonic injection into a ring-VCO requires a pulse generator, which enhances harmonics but generates large reference spurs. Besides, a race condition between the injection-locking path and the PLL path weakens the locking strength and prolongs settling time by 5 times [2]. In order to reject the phase noise and to minimize supply sensitivity and frequency drift of ring-VCO-based PLLs without compromising other parameters, this paper proposes a 3rd-order PLL employing a cascaded time-amplified clock-skew-sub-sampling DLL, measuring a 4.2μs settling time, 1.05ps integrated jitter, and -113dBc/Hz in-band phase noise with a 3.84mW power consumption at a 2.1GHz output frequency.