3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC

Jeffrey Ho; Howard Cam Luong

3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC

Jeffrey Ho^*, Howard Cam Luong

^*Corresponding author for this work

Department of Electronic and Computer Engineering

Research output: Contribution to conference › Conference Paper › peer-review

11 Citations (Scopus)

Abstract

A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8μm technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at v_i+, DC at v_i-, and a clock frequency of 120 MHz, the measured rise-time, fall-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. Optimization issue of the comparator is discussed.

Original language	English
Pages	413-416
Number of pages	4
Publication status	Published - 1996
Event	Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea Duration: 18 Nov 1996 → 21 Nov 1996

Conference

Conference	Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems
City	Seoul, South Korea
Period	18/11/96 → 21/11/96

Cite this

@conference{2d1d99e94da54037aba4ca9bf5d724bf,

title = "3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC",

abstract = "A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8μm technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at vi+, DC at vi-, and a clock frequency of 120 MHz, the measured rise-time, fall-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. Optimization issue of the comparator is discussed.",

author = "Jeffrey Ho and Luong, \{Howard Cam\}",

year = "1996",

language = "English",

pages = "413--416",

note = "Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 18-11-1996 Through 21-11-1996",

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TY - CONF

T1 - 3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC

AU - Ho, Jeffrey

AU - Luong, Howard Cam

PY - 1996

Y1 - 1996

N2 - A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8μm technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at vi+, DC at vi-, and a clock frequency of 120 MHz, the measured rise-time, fall-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. Optimization issue of the comparator is discussed.

AB - A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8μm technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at vi+, DC at vi-, and a clock frequency of 120 MHz, the measured rise-time, fall-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. Optimization issue of the comparator is discussed.

UR - https://www.scopus.com/pages/publications/0030407738

M3 - Conference Paper

AN - SCOPUS:0030407738

SP - 413

EP - 416

T2 - Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 18 November 1996 through 21 November 1996

ER -

3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC

Abstract

Conference

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