750MS/S NMOS LATCHED COMPARATOR.

David C. Soo; Alexander M. Voshchenkov; Gen M. Chin; Vance D. Archer; Maureen Lau; Mark Morris; Ping K. Ko; Robert G. Meyer; Bruce A. Wooley

750MS/S NMOS LATCHED COMPARATOR.

David C. Soo^*, Alexander M. Voshchenkov, Gen M. Chin, Vance D. Archer, Maureen Lau, Mark Morris, Ping K. Ko, Robert G. Meyer, Bruce A. Wooley

^*Corresponding author for this work

Research output: Contribution to journal › Conference article published in journal › peer-review

8 Citations (Scopus)

Abstract

Summary form only given. The design of analog circuits integrated in a polysilicon gate NMOS technology with 1 mu m effective channel length devices is described. In particular, a latched comparator with 4-b input resolution at 750 MS/s and a wideband amplifier with 10 dB of voltage gain over a bandwidth of 1. 25 GHz, when driving 130 fF of on-chip capacitance, are reported. The comparator was designed primarily for application to high-speed flash A/D conversion, but is also suitable for use in integrated broadband fiber-optic receivers. Its circuit configuration differs from previous designs in that negative feedback is used in the preamplifier section to trade gain for bandwidth.

Original language	English
Pages (from-to)	146-147, 327
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication status	Published - 1985
Externally published	Yes

Cite this

@article{86bd957006a648c695b8275f60fe3a4e,

title = "750MS/S NMOS LATCHED COMPARATOR.",

abstract = "Summary form only given. The design of analog circuits integrated in a polysilicon gate NMOS technology with 1 mu m effective channel length devices is described. In particular, a latched comparator with 4-b input resolution at 750 MS/s and a wideband amplifier with 10 dB of voltage gain over a bandwidth of 1. 25 GHz, when driving 130 fF of on-chip capacitance, are reported. The comparator was designed primarily for application to high-speed flash A/D conversion, but is also suitable for use in integrated broadband fiber-optic receivers. Its circuit configuration differs from previous designs in that negative feedback is used in the preamplifier section to trade gain for bandwidth.",

author = "Soo, \{David C.\} and Voshchenkov, \{Alexander M.\} and Chin, \{Gen M.\} and Archer, \{Vance D.\} and Maureen Lau and Mark Morris and Ko, \{Ping K.\} and Meyer, \{Robert G.\} and Wooley, \{Bruce A.\}",

year = "1985",

language = "English",

pages = "146--147, 327",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - 750MS/S NMOS LATCHED COMPARATOR.

AU - Soo, David C.

AU - Voshchenkov, Alexander M.

AU - Chin, Gen M.

AU - Archer, Vance D.

AU - Lau, Maureen

AU - Morris, Mark

AU - Ko, Ping K.

AU - Meyer, Robert G.

AU - Wooley, Bruce A.

PY - 1985

Y1 - 1985

N2 - Summary form only given. The design of analog circuits integrated in a polysilicon gate NMOS technology with 1 mu m effective channel length devices is described. In particular, a latched comparator with 4-b input resolution at 750 MS/s and a wideband amplifier with 10 dB of voltage gain over a bandwidth of 1. 25 GHz, when driving 130 fF of on-chip capacitance, are reported. The comparator was designed primarily for application to high-speed flash A/D conversion, but is also suitable for use in integrated broadband fiber-optic receivers. Its circuit configuration differs from previous designs in that negative feedback is used in the preamplifier section to trade gain for bandwidth.

AB - Summary form only given. The design of analog circuits integrated in a polysilicon gate NMOS technology with 1 mu m effective channel length devices is described. In particular, a latched comparator with 4-b input resolution at 750 MS/s and a wideband amplifier with 10 dB of voltage gain over a bandwidth of 1. 25 GHz, when driving 130 fF of on-chip capacitance, are reported. The comparator was designed primarily for application to high-speed flash A/D conversion, but is also suitable for use in integrated broadband fiber-optic receivers. Its circuit configuration differs from previous designs in that negative feedback is used in the preamplifier section to trade gain for bandwidth.

UR - https://www.scopus.com/pages/publications/0022182973

M3 - Conference article published in journal

AN - SCOPUS:0022182973

SN - 0193-6530

SP - 146-147, 327

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

ER -

750MS/S NMOS LATCHED COMPARATOR.

Abstract

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