Abstract
A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented. Novel circuit designs are demonstrated in the system for low-voltage applications including design of voltage-controlled oscillator and design of programmable divider. Implemented in a 0.18-μm CMOS process and operated at 1-V supply voltage, the synthesizer measures phase noise of -136 dBc/Hz at a frequency offset of 20 MHz and spur performance of less than -80 dBc at an offset of 11 MHz. The synthesizer dissipates 27.5 mW from a single 1-V supply and occupies a chip area of 1.03 mm2.
| Original language | English |
|---|---|
| Pages (from-to) | 1873-1882 |
| Number of pages | 10 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 39 |
| Issue number | 11 |
| DOIs | |
| Publication status | Published - Nov 2004 |
Keywords
- Clock generation
- Integer-N
- Low power
- Low voltage
- Oscillator
- Phase-locked loop (PLL)
- Receiver
- Synthesizer
- Transceiver
- VCO
- WLAN
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