A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs

Jaejin Park; Ruifeng Sun; L. Richard Carley; C. Patrick Yue

doi:10.1109/ISCAS.2005.1464800

A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs

Jaejin Park^*, Ruifeng Sun, L. Richard Carley, C. Patrick Yue

^*Corresponding author for this work

Research output: Contribution to journal › Conference article published in journal › peer-review

7 Citations (Scopus)

Abstract

This paper presents a new system architecture for future hard disk channel ICs based on a high-speed digital parallel interface. A crosstalk cancellation technique using a novel data encoding scheme is proposed to suppress electromagnetic interference (EMI) generated by the I/Os. This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. Simulations show a 37% crosstalk reduction for six adjacent channels each operating at 10 Gbps. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-ím digital CMOS process, the transceiver excluding the test logic consumes 310 mW from a 1-V supply based on simulation results.

Original language	English
Article number	1464800
Pages (from-to)	1162-1165
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464800
Publication status	Published - 2005
Externally published	Yes
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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10.1109/ISCAS.2005.1464800

Cite this

@article{8d1e998061444215a701fe71921f876e,

title = "A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs",

abstract = "This paper presents a new system architecture for future hard disk channel ICs based on a high-speed digital parallel interface. A crosstalk cancellation technique using a novel data encoding scheme is proposed to suppress electromagnetic interference (EMI) generated by the I/Os. This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. Simulations show a 37\% crosstalk reduction for six adjacent channels each operating at 10 Gbps. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-{\'i}m digital CMOS process, the transceiver excluding the test logic consumes 310 mW from a 1-V supply based on simulation results.",

author = "Jaejin Park and Ruifeng Sun and Carley, \{L. Richard\} and Yue, \{C. Patrick\}",

year = "2005",

doi = "10.1109/ISCAS.2005.1464800",

language = "English",

pages = "1162--1165",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

}

TY - JOUR

T1 - A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs

AU - Park, Jaejin

AU - Sun, Ruifeng

AU - Carley, L. Richard

AU - Yue, C. Patrick

PY - 2005

Y1 - 2005

N2 - This paper presents a new system architecture for future hard disk channel ICs based on a high-speed digital parallel interface. A crosstalk cancellation technique using a novel data encoding scheme is proposed to suppress electromagnetic interference (EMI) generated by the I/Os. This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. Simulations show a 37% crosstalk reduction for six adjacent channels each operating at 10 Gbps. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-ím digital CMOS process, the transceiver excluding the test logic consumes 310 mW from a 1-V supply based on simulation results.

AB - This paper presents a new system architecture for future hard disk channel ICs based on a high-speed digital parallel interface. A crosstalk cancellation technique using a novel data encoding scheme is proposed to suppress electromagnetic interference (EMI) generated by the I/Os. This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. Simulations show a 37% crosstalk reduction for six adjacent channels each operating at 10 Gbps. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-ím digital CMOS process, the transceiver excluding the test logic consumes 310 mW from a 1-V supply based on simulation results.

UR - https://openalex.org/W1586613304

UR - https://www.scopus.com/pages/publications/39549105739

U2 - 10.1109/ISCAS.2005.1464800

DO - 10.1109/ISCAS.2005.1464800

M3 - Conference article published in journal

SN - 0271-4310

SP - 1162

EP - 1165

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1464800

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs

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