A 116-132GHz -193.6dBc/Hz-FoMT -252.8dB-FoMJ Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler

Zhiyu LIU; Howard Cam LUONG

doi:10.1109/RFIC61188.2025.11082924

A 116-132GHz -193.6dBc/Hz-FoM_T -252.8dB-FoM_J Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler

Zhiyu LIU^*, Howard Cam LUONG

^*Corresponding author for this work

Department of Electronic and Computer Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

Abstract

A wide-tuning-range (TR) low-phase-noise (PN) D-band frequency synthesizer cascades a mm-Wave double-sampling PLL (DSPLL) with a D-band differential-output injection-locked frequency doubler (ILFM × 2). DSPLL consists of a dual-band VCO (DBVCO) with magnetic parabolic tuning and split primary coils, an injection-locked frequency divider (ILFD), and a superior double-sampling phase detector (DSPD) enabling a dual-path loop filter. ILFM × 2 features differential outputs, self-oscillation current boosting, and center-tap injection. Fabricated in a 28-nm CMOS, the synthesizer measures TR of 12.9% from 116 to 132G, PN@1M normalized to 120G of -92.9-106.1dBc/Hz, jitter (1 k-100 M) of 35.1-145.3fs, FoM_T @ 1 M of -180.6 ∼-193.6 dBc / Hz, and FoM_J of -240.3-252.8dB.

Original language	English
Title of host publication	2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025
Editors	Jane Gu, Kenichi Okada
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	335-338
Number of pages	4
ISBN (Electronic)	9798331514112
DOIs	https://doi.org/10.1109/RFIC61188.2025.11082924
Publication status	Published - 24 Jul 2025
Event	2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025 - San Francisco, United States Duration: 15 Jun 2025 → 17 Jun 2025

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)	1529-2517

Conference

Conference	2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025
Country/Territory	United States
City	San Francisco
Period	15/06/25 → 17/06/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

CMOS
D-band
ILFD
ILFM
PLL
VCO
double-sampling
frequency synthesizer
parabolic tuning

Access to Document

10.1109/RFIC61188.2025.11082924

Cite this

LIU, Z., & LUONG, H. C. (2025). A 116-132GHz -193.6dBc/Hz-FoM_T -252.8dB-FoM_J Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler. In J. Gu, & K. Okada (Eds.), 2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025 (pp. 335-338). (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIC61188.2025.11082924

LIU, Zhiyu ; LUONG, Howard Cam. / A 116-132GHz -193.6dBc/Hz-FoM_T -252.8dB-FoM_J Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler. 2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025. editor / Jane Gu ; Kenichi Okada. Institute of Electrical and Electronics Engineers Inc., 2025. pp. 335-338 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

@inproceedings{6fd48adf386446a7ba20570cacb53389,

title = "A 116-132GHz -193.6dBc/Hz-FoMT -252.8dB-FoMJ Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler",

abstract = "A wide-tuning-range (TR) low-phase-noise (PN) D-band frequency synthesizer cascades a mm-Wave double-sampling PLL (DSPLL) with a D-band differential-output injection-locked frequency doubler (ILFM × 2). DSPLL consists of a dual-band VCO (DBVCO) with magnetic parabolic tuning and split primary coils, an injection-locked frequency divider (ILFD), and a superior double-sampling phase detector (DSPD) enabling a dual-path loop filter. ILFM × 2 features differential outputs, self-oscillation current boosting, and center-tap injection. Fabricated in a 28-nm CMOS, the synthesizer measures TR of 12.9\% from 116 to 132G, PN@1M normalized to 120G of -92.9-106.1dBc/Hz, jitter (1 k-100 M) of 35.1-145.3fs, FoMT @ 1 M of -180.6 ∼-193.6 dBc / Hz, and FoMJ of -240.3-252.8dB.",

keywords = "CMOS, D-band, ILFD, ILFM, PLL, VCO, double-sampling, frequency synthesizer, parabolic tuning",

author = "Zhiyu LIU and LUONG, \{Howard Cam\}",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025 ; Conference date: 15-06-2025 Through 17-06-2025",

year = "2025",

month = jul,

day = "24",

doi = "10.1109/RFIC61188.2025.11082924",

language = "English",

series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

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LIU, Z & LUONG, HC 2025, A 116-132GHz -193.6dBc/Hz-FoM_T -252.8dB-FoM_J Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler. in J Gu & K Okada (eds), 2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025. Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, Institute of Electrical and Electronics Engineers Inc., pp. 335-338, 2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025, San Francisco, United States, 15/06/25. https://doi.org/10.1109/RFIC61188.2025.11082924

A 116-132GHz -193.6dBc/Hz-FoM_T -252.8dB-FoM_J Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler. / LIU, Zhiyu; LUONG, Howard Cam.
2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025. ed. / Jane Gu; Kenichi Okada. Institute of Electrical and Electronics Engineers Inc., 2025. p. 335-338 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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AB - A wide-tuning-range (TR) low-phase-noise (PN) D-band frequency synthesizer cascades a mm-Wave double-sampling PLL (DSPLL) with a D-band differential-output injection-locked frequency doubler (ILFM × 2). DSPLL consists of a dual-band VCO (DBVCO) with magnetic parabolic tuning and split primary coils, an injection-locked frequency divider (ILFD), and a superior double-sampling phase detector (DSPD) enabling a dual-path loop filter. ILFM × 2 features differential outputs, self-oscillation current boosting, and center-tap injection. Fabricated in a 28-nm CMOS, the synthesizer measures TR of 12.9% from 116 to 132G, PN@1M normalized to 120G of -92.9-106.1dBc/Hz, jitter (1 k-100 M) of 35.1-145.3fs, FoMT @ 1 M of -180.6 ∼-193.6 dBc / Hz, and FoMJ of -240.3-252.8dB.

KW - CMOS

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KW - ILFM

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KW - VCO

KW - double-sampling

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KW - parabolic tuning

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T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

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BT - 2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025

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LIU Z, LUONG HC. A 116-132GHz -193.6dBc/Hz-FoM_T -252.8dB-FoM_J Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler. In Gu J, Okada K, editors, 2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025. Institute of Electrical and Electronics Engineers Inc. 2025. p. 335-338. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). doi: 10.1109/RFIC61188.2025.11082924