@inproceedings{0a617e7825944437b7a7ce8d024a4d33,
title = "A 20MHz switched-current sample-and-hold circuit for current mode analog iterative decoders",
abstract = "A high-frequency low-power switched-current (SI) sample-and-hold (S/H) of a current-mode analog iterative decoder is proposed. A capacitor divider is used to reduce charge injection from the sampling switch and a cascode transistor is used to reduce channel length modulation. The cascode transistor is biased by a CMOS peaking current source rather than the conventional CMOS Widlar current source to arrive at stable S/H operation. The SI S/H is designed using a 0.35 μm CMOS process, and simulation results show that it could operate at 20MHz, consuming a power of only 22.275 μW.",
keywords = "Analog iterative decoder, Sample-and-hold, Supply-independent current source, Switched-current",
author = "Lo, \{Ming Yam\} and Ki, \{Wing Hung\} and Mow, \{Wai Ho\}",
year = "2009",
language = "English",
isbn = "9789810824686",
series = "ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings",
pages = "283--286",
booktitle = "ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings",
note = "12th International Symposium on Integrated Circuits, ISIC-2009 ; Conference date: 14-12-2009 Through 16-12-2009",
}