A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator

Zhao Zhang; Guang Zhu; Can Wang; Li Wang; C. Patrick Yue

doi:10.1109/A-SSCC47793.2019.9056913

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator

Zhao Zhang, Guang Zhu, Can Wang, Li Wang, C. Patrick Yue

Department of Electronic and Computer Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

3 Citations (Scopus)

Abstract

This paper presents a low-power low-jitter PAM4 clock and data recovery circuit. A novel quarter-rate linear phase detector (QLPD) is proposed to lower the recovered clock jitter. A self-biased PLL based multiphase clock generator (MCG) is proposed to reduce power consumption. Fabricated in 40-nm CMOS process, the prototype achieves error-free operation at 32-Gb/s input data rate with 0.46-pJ/bit bit efficiency and 352.6-fs integrated jitter of the 4-GHz recovered clock. The measured jitter tolerance at BER of < 10^-12 is higher than 0.35 UI_PP with the corner frequency at about 10 MHz.

Original language	English
Title of host publication	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	241-242
Number of pages	2
ISBN (Electronic)	9781728151069
DOIs	https://doi.org/10.1109/A-SSCC47793.2019.9056913
Publication status	Published - Nov 2019
Event	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China Duration: 4 Nov 2019 → 6 Nov 2019

Publication series

Name	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Conference

Conference	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/Territory	China
City	Macao
Period	4/11/19 → 6/11/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

PAM CDR
low-power
multiphase clock generator
quarter-rate linear phase detector
self-biased PLL

Access to Document

10.1109/A-SSCC47793.2019.9056913

Cite this

Zhang, Z., Zhu, G., Wang, C., Wang, L., & Yue, C. P. (2019). A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 (pp. 241-242). Article 9056913 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC47793.2019.9056913

Zhang, Zhao ; Zhu, Guang ; Wang, Can et al. / A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 241-242 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019).

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title = "A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator",

abstract = "This paper presents a low-power low-jitter PAM4 clock and data recovery circuit. A novel quarter-rate linear phase detector (QLPD) is proposed to lower the recovered clock jitter. A self-biased PLL based multiphase clock generator (MCG) is proposed to reduce power consumption. Fabricated in 40-nm CMOS process, the prototype achieves error-free operation at 32-Gb/s input data rate with 0.46-pJ/bit bit efficiency and 352.6-fs integrated jitter of the 4-GHz recovered clock. The measured jitter tolerance at BER of < 10-12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz.",

keywords = "PAM CDR, low-power, multiphase clock generator, quarter-rate linear phase detector, self-biased PLL",

author = "Zhao Zhang and Guang Zhu and Can Wang and Li Wang and Yue, \{C. Patrick\}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 ; Conference date: 04-11-2019 Through 06-11-2019",

year = "2019",

month = nov,

doi = "10.1109/A-SSCC47793.2019.9056913",

language = "English",

series = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "241--242",

booktitle = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",

}

Zhang, Z, Zhu, G, Wang, C, Wang, L & Yue, CP 2019, A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. in Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019., 9056913, Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Institute of Electrical and Electronics Engineers Inc., pp. 241-242, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macao, China, 4/11/19. https://doi.org/10.1109/A-SSCC47793.2019.9056913

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. / Zhang, Zhao; Zhu, Guang; Wang, Can et al.
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 241-242 9056913 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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T1 - A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator

AU - Zhang, Zhao

AU - Zhu, Guang

AU - Wang, Can

AU - Wang, Li

AU - Yue, C. Patrick

PY - 2019/11

Y1 - 2019/11

N2 - This paper presents a low-power low-jitter PAM4 clock and data recovery circuit. A novel quarter-rate linear phase detector (QLPD) is proposed to lower the recovered clock jitter. A self-biased PLL based multiphase clock generator (MCG) is proposed to reduce power consumption. Fabricated in 40-nm CMOS process, the prototype achieves error-free operation at 32-Gb/s input data rate with 0.46-pJ/bit bit efficiency and 352.6-fs integrated jitter of the 4-GHz recovered clock. The measured jitter tolerance at BER of < 10-12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz.

AB - This paper presents a low-power low-jitter PAM4 clock and data recovery circuit. A novel quarter-rate linear phase detector (QLPD) is proposed to lower the recovered clock jitter. A self-biased PLL based multiphase clock generator (MCG) is proposed to reduce power consumption. Fabricated in 40-nm CMOS process, the prototype achieves error-free operation at 32-Gb/s input data rate with 0.46-pJ/bit bit efficiency and 352.6-fs integrated jitter of the 4-GHz recovered clock. The measured jitter tolerance at BER of < 10-12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz.

KW - PAM CDR

KW - low-power

KW - multiphase clock generator

KW - quarter-rate linear phase detector

KW - self-biased PLL

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DO - 10.1109/A-SSCC47793.2019.9056913

M3 - Conference Paper published in a book

T3 - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

SP - 241

EP - 242

BT - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Y2 - 4 November 2019 through 6 November 2019

ER -

Zhang Z, Zhu G, Wang C, Wang L, Yue CP. A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 241-242. 9056913. (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). doi: 10.1109/A-SSCC47793.2019.9056913

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator

Abstract

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Bibliographical note

Keywords

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