A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator
- Zhao Zhang
- , Guang Zhu
- , Can Wang
- , Li Wang
- , C. Patrick Yue
Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review
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