A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2 nd-order noise-shaping TDC and a transformer-coupled QVCO

Alan W.L. Ng; Shiyuan Zheng; Howard C. Luong

doi:10.1109/ESSCIRC.2012.6341290

A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2 ^nd-order noise-shaping TDC and a transformer-coupled QVCO

Alan W.L. Ng^*, Shiyuan Zheng, Howard C. Luong

^*Corresponding author for this work

Department of Electronic and Computer Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

10 Citations (Scopus)

Abstract

A 4.1GHz-6.5GHz all-digital fractional-n frequency synthesizer is presented employing a 2^nd-order noise-shaping time-to-digital converter (TDC) and an embedded-FIR-filter transformer-coupled quadrature digitally-control oscillator (QDCO). Implemented in a 65nm CMOS, the prototype measures phase noise of 100dBc/Hz in-band and 145dBc/Hz at 20MHz offset from a 4.5GHz carrier while consuming 26mW from 1.2V supply and occupying 1mm². The IQ phase error is smaller than 1.2°

Original language	English
Title of host publication	2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
Pages	189-192
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2012.6341290
Publication status	Published - 2012
Event	38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France Duration: 17 Sept 2012 → 21 Sept 2012

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	38th European Solid State Circuits Conference, ESSCIRC 2012
Country/Territory	France
City	Bordeaux
Period	17/09/12 → 21/09/12

Access to Document

10.1109/ESSCIRC.2012.6341290

Cite this

@inproceedings{de3d40b6ef934fd58ff50e694bb1a2ba,

title = "A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2 nd-order noise-shaping TDC and a transformer-coupled QVCO",

abstract = "A 4.1GHz-6.5GHz all-digital fractional-n frequency synthesizer is presented employing a 2nd-order noise-shaping time-to-digital converter (TDC) and an embedded-FIR-filter transformer-coupled quadrature digitally-control oscillator (QDCO). Implemented in a 65nm CMOS, the prototype measures phase noise of 100dBc/Hz in-band and 145dBc/Hz at 20MHz offset from a 4.5GHz carrier while consuming 26mW from 1.2V supply and occupying 1mm2. The IQ phase error is smaller than 1.2°",

author = "Ng, \{Alan W.L.\} and Shiyuan Zheng and Luong, \{Howard C.\}",

year = "2012",

doi = "10.1109/ESSCIRC.2012.6341290",

language = "English",

isbn = "9781467322126",

series = "European Solid-State Circuits Conference",

pages = "189--192",

booktitle = "2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012",

note = "38th European Solid State Circuits Conference, ESSCIRC 2012 ; Conference date: 17-09-2012 Through 21-09-2012",

}

Ng, AWL, Zheng, S & Luong, HC 2012, A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2 ^nd-order noise-shaping TDC and a transformer-coupled QVCO. in 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012., 6341290, European Solid-State Circuits Conference, pp. 189-192, 38th European Solid State Circuits Conference, ESSCIRC 2012, Bordeaux, France, 17/09/12. https://doi.org/10.1109/ESSCIRC.2012.6341290

A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2 ^nd-order noise-shaping TDC and a transformer-coupled QVCO. / Ng, Alan W.L.; Zheng, Shiyuan; Luong, Howard C.
2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. 2012. p. 189-192 6341290 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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