A 5–10-GHz Quadrature Clock Generator With Open-Loop Quadrature Error Correction in 28-nm CMOS

This letter introduces the design of a 4-phase quadrature clock generator (QCG) featuring digital automatic calibration. The QCG architecture comprises a duty cycle correction (DCC) circuit, a digitally controlled delay line (DCDL), and an open-loop quadrature error correction (QEC) circuit utilizing phase interpolators (PIs). The DCDL generates clock signals with an initial coarse quadrature phase error, which is subsequently refined by the QEC to achieve a phase error of less than 1°. A finite state machine (FSM) conducts background calibration for the DCC and DCDL coarse correction, employing a pattern-detecting strategy to disable calibration, thereby eliminating spurious tones and deterministic jitter from the output clocks. Measurement results demonstrate that the proposed QCG achieves a phase error below 0.8° across a frequency range of 5–10 GHz, with an integrated jitter of 61.1 fs and a power consumption of 10.2 mW at 10-GHz operation.