A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

Can Wang; Guang Zhu; Zhao Zhang; C. Patrick Yue

doi:10.23919/VLSIC.2019.8778159

A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

Can Wang, Guang Zhu, Zhao Zhang, C. Patrick Yue

Department of Electronic and Computer Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

16 Citations (Scopus)

Abstract

This paper presents a source-synchronous PAM4 receiver that adopts quarter-rate topology to achieve good bit efficiency and a voltage-controlled delay line (VCDL) in the reference path of a phase-locked loop (PLL) to recover clock and data. With linear quarter-rate samplers, the equalized input signal by two-stage continuous-time linear equalizer (CTLE) is further equalized by 1tap feed forward equalizer (FFE) embedded in the sampler, and then processed by the following power-efficient dynamic latch and CMOS logics. With the VCDL adjusted by a bang-bang phase detector (BBPD) and a charge pump (CP), the output clocks of the four-stage ring oscillator (RO) based PLL have equal phase spacing and track the input data accordingly. The 40-nm CMOS receiver IC achieves error-free operation at 52 Gb/s with a superior bit efficiency of 0.92 pJ/b while compensating for 7.3-dB channel loss at 13 GHz.

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C274-C275
ISBN (Electronic)	9784863487185
DOIs	https://doi.org/10.23919/VLSIC.2019.8778159
Publication status	Published - Jun 2019
Event	33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2019-June

Conference

Conference	33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

Bibliographical note

Publisher Copyright:
© 2019 JSAP.

Access to Document

10.23919/VLSIC.2019.8778159

Cite this

Wang, C., Zhu, G., Zhang, Z., & Yue, C. P. (2019). A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (pp. C274-C275). Article 8778159 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2019.8778159

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title = "A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects",

abstract = "This paper presents a source-synchronous PAM4 receiver that adopts quarter-rate topology to achieve good bit efficiency and a voltage-controlled delay line (VCDL) in the reference path of a phase-locked loop (PLL) to recover clock and data. With linear quarter-rate samplers, the equalized input signal by two-stage continuous-time linear equalizer (CTLE) is further equalized by 1tap feed forward equalizer (FFE) embedded in the sampler, and then processed by the following power-efficient dynamic latch and CMOS logics. With the VCDL adjusted by a bang-bang phase detector (BBPD) and a charge pump (CP), the output clocks of the four-stage ring oscillator (RO) based PLL have equal phase spacing and track the input data accordingly. The 40-nm CMOS receiver IC achieves error-free operation at 52 Gb/s with a superior bit efficiency of 0.92 pJ/b while compensating for 7.3-dB channel loss at 13 GHz.",

author = "Can Wang and Guang Zhu and Zhao Zhang and Yue, \{C. Patrick\}",

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Wang, C, Zhu, G, Zhang, Z & Yue, CP 2019, A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers., 8778159, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. C274-C275, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIC.2019.8778159

A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. / Wang, Can; Zhu, Guang; Zhang, Zhao et al.
2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. C274-C275 8778159 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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N2 - This paper presents a source-synchronous PAM4 receiver that adopts quarter-rate topology to achieve good bit efficiency and a voltage-controlled delay line (VCDL) in the reference path of a phase-locked loop (PLL) to recover clock and data. With linear quarter-rate samplers, the equalized input signal by two-stage continuous-time linear equalizer (CTLE) is further equalized by 1tap feed forward equalizer (FFE) embedded in the sampler, and then processed by the following power-efficient dynamic latch and CMOS logics. With the VCDL adjusted by a bang-bang phase detector (BBPD) and a charge pump (CP), the output clocks of the four-stage ring oscillator (RO) based PLL have equal phase spacing and track the input data accordingly. The 40-nm CMOS receiver IC achieves error-free operation at 52 Gb/s with a superior bit efficiency of 0.92 pJ/b while compensating for 7.3-dB channel loss at 13 GHz.

AB - This paper presents a source-synchronous PAM4 receiver that adopts quarter-rate topology to achieve good bit efficiency and a voltage-controlled delay line (VCDL) in the reference path of a phase-locked loop (PLL) to recover clock and data. With linear quarter-rate samplers, the equalized input signal by two-stage continuous-time linear equalizer (CTLE) is further equalized by 1tap feed forward equalizer (FFE) embedded in the sampler, and then processed by the following power-efficient dynamic latch and CMOS logics. With the VCDL adjusted by a bang-bang phase detector (BBPD) and a charge pump (CP), the output clocks of the four-stage ring oscillator (RO) based PLL have equal phase spacing and track the input data accordingly. The 40-nm CMOS receiver IC achieves error-free operation at 52 Gb/s with a superior bit efficiency of 0.92 pJ/b while compensating for 7.3-dB channel loss at 13 GHz.

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Wang C, Zhu G, Zhang Z, Yue CP. A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. C274-C275. 8778159. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2019.8778159

A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

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