TY - GEN
T1 - A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical
AU - Pan, Quan
AU - Hou, Zhengxiong
AU - Wang, Yipeng
AU - Yue, C. Patrick
PY - 2013
Y1 - 2013
N2 - A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.
AB - A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.
KW - Avalanche photodetector
KW - CMOS Photodetector
KW - CMOS integrated optical receiver
UR - https://openalex.org/W2041945451
UR - https://www.scopus.com/pages/publications/84901293387
U2 - 10.1109/ASICON.2013.6811921
DO - 10.1109/ASICON.2013.6811921
M3 - Conference Paper published in a book
SN - 9781467364157
T3 - Proceedings of International Conference on ASIC
BT - 2013 IEEE 10th International Conference on ASIC, ASICON 2013
PB - IEEE Computer Society
T2 - 2013 IEEE 10th International Conference on ASIC, ASICON 2013
Y2 - 28 October 2013 through 31 October 2013
ER -