A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO

Yi Liu; Zixi Jing; Zhiyu Liu; Chi C. Yip; Zhirui Zong; Howard C. Luong

doi:10.1109/RFIC61187.2024.10600027

A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO

Yi Liu^*, Zixi Jing, Zhiyu Liu, Chi C. Yip, Zhirui Zong, Howard C. Luong

^*Corresponding author for this work

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

5 Citations (Scopus)

Abstract

A 74-80 GHz self-adapted sawtooth-FMCW frequency synthesizer features a Type-II digital PLL with zero TDC offset independent of chirp rate, TDC-gain-independent loop bandwidth, a 25kHz-resolution glitch-free wideband linear digitally controlled oscillator (DCO) with a dedicated convergence-less digital pre-distortion (DPD). The prototype measures 6-GHz chirp bandwidth with a 1.2GHz/us slope at 77GHz while achieving 0.031% rms chirp error and consuming 20.9mW from 0.9V supply.

Original language	English
Title of host publication	2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	207-210
Number of pages	4
ISBN (Electronic)	9798350359473
DOIs	https://doi.org/10.1109/RFIC61187.2024.10600027
Publication status	Published - 2024
Event	2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024 - Washington, United States Duration: 16 Jun 2024 → 18 Jun 2024

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)	1529-2517

Conference

Conference	2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024
Country/Territory	United States
City	Washington
Period	16/06/24 → 18/06/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

Keywords

Bang-Bang TDC
FMCW frequency synthesizer
Type-II Digital PLL
magnetic tuning

Access to Document

10.1109/RFIC61187.2024.10600027

Cite this

Liu, Y., Jing, Z., Liu, Z., Yip, C. C., Zong, Z., & Luong, H. C. (2024). A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO. In 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024 (pp. 207-210). (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIC61187.2024.10600027

Liu, Yi ; Jing, Zixi ; Liu, Zhiyu et al. / A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO. 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024. Institute of Electrical and Electronics Engineers Inc., 2024. pp. 207-210 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

@inproceedings{23bbd07363be429190724d054adb2c6c,

title = "A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO",

abstract = "A 74-80 GHz self-adapted sawtooth-FMCW frequency synthesizer features a Type-II digital PLL with zero TDC offset independent of chirp rate, TDC-gain-independent loop bandwidth, a 25kHz-resolution glitch-free wideband linear digitally controlled oscillator (DCO) with a dedicated convergence-less digital pre-distortion (DPD). The prototype measures 6-GHz chirp bandwidth with a 1.2GHz/us slope at 77GHz while achieving 0.031\% rms chirp error and consuming 20.9mW from 0.9V supply.",

keywords = "Bang-Bang TDC, FMCW frequency synthesizer, Type-II Digital PLL, magnetic tuning",

author = "Yi Liu and Zixi Jing and Zhiyu Liu and Yip, \{Chi C.\} and Zhirui Zong and Luong, \{Howard C.\}",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024 ; Conference date: 16-06-2024 Through 18-06-2024",

year = "2024",

doi = "10.1109/RFIC61187.2024.10600027",

language = "English",

series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "207--210",

booktitle = "2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024",

}

Liu, Y, Jing, Z, Liu, Z, Yip, CC, Zong, Z & Luong, HC 2024, A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO. in 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024. Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, Institute of Electrical and Electronics Engineers Inc., pp. 207-210, 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024, Washington, United States, 16/06/24. https://doi.org/10.1109/RFIC61187.2024.10600027

A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO. / Liu, Yi; Jing, Zixi; Liu, Zhiyu et al.
2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024. Institute of Electrical and Electronics Engineers Inc., 2024. p. 207-210 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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AU - Liu, Yi

AU - Jing, Zixi

AU - Liu, Zhiyu

AU - Yip, Chi C.

AU - Zong, Zhirui

AU - Luong, Howard C.

PY - 2024

Y1 - 2024

N2 - A 74-80 GHz self-adapted sawtooth-FMCW frequency synthesizer features a Type-II digital PLL with zero TDC offset independent of chirp rate, TDC-gain-independent loop bandwidth, a 25kHz-resolution glitch-free wideband linear digitally controlled oscillator (DCO) with a dedicated convergence-less digital pre-distortion (DPD). The prototype measures 6-GHz chirp bandwidth with a 1.2GHz/us slope at 77GHz while achieving 0.031% rms chirp error and consuming 20.9mW from 0.9V supply.

AB - A 74-80 GHz self-adapted sawtooth-FMCW frequency synthesizer features a Type-II digital PLL with zero TDC offset independent of chirp rate, TDC-gain-independent loop bandwidth, a 25kHz-resolution glitch-free wideband linear digitally controlled oscillator (DCO) with a dedicated convergence-less digital pre-distortion (DPD). The prototype measures 6-GHz chirp bandwidth with a 1.2GHz/us slope at 77GHz while achieving 0.031% rms chirp error and consuming 20.9mW from 0.9V supply.

KW - Bang-Bang TDC

KW - FMCW frequency synthesizer

KW - Type-II Digital PLL

KW - magnetic tuning

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DO - 10.1109/RFIC61187.2024.10600027

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T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

SP - 207

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BT - 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024

Y2 - 16 June 2024 through 18 June 2024

ER -

Liu Y, Jing Z, Liu Z, Yip CC, Zong Z, Luong HC. A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO. In 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024. Institute of Electrical and Electronics Engineers Inc. 2024. p. 207-210. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). doi: 10.1109/RFIC61187.2024.10600027

A 74GHz-80GHz 1.2GHz/μs-Slope 20.9mW FMCW Synthesizer with TDC-Gain-Independent Loop-Bandwidth Employing a TDC-Offset- Free Type-II Digital PLL and a Linearized Hybrid-Tuning DCO

Abstract

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