A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation

Ka Nang Leung; Philip K.T. Mok

doi:10.1109/JSSC.2003.817256

A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation

Ka Nang Leung^*, Philip K.T. Mok

^*Corresponding author for this work

Department of Electronic and Computer Engineering

Research output: Contribution to journal › Journal Article › peer-review

446 Citations (Scopus)

Abstract

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-μm CMOS technology, and the active chip area is 568 μm × 541 μm. The total error of the output voltage due to line and load variations is less than ±0.25%, and the temperature coefficient is 38 ppm/°C. Moreover, the output voltage can recover within 2 μs for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 μV/√Hz, respectively.

Original language	English
Pages (from-to)	1691-1702
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	38
Issue number	10
DOIs	https://doi.org/10.1109/JSSC.2003.817256
Publication status	Published - Oct 2003

Keywords

CMOS voltage reference
Capacitor-free low-dropout regulator (LDO)
Damping-factor-control frequency compensation
Loop-gain stability

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10.1109/JSSC.2003.817256

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title = "A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation",

abstract = "A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-μm CMOS technology, and the active chip area is 568 μm × 541 μm. The total error of the output voltage due to line and load variations is less than ±0.25\%, and the temperature coefficient is 38 ppm/°C. Moreover, the output voltage can recover within 2 μs for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 μV/√Hz, respectively.",

keywords = "CMOS voltage reference, Capacitor-free low-dropout regulator (LDO), Damping-factor-control frequency compensation, Loop-gain stability",

author = "Leung, \{Ka Nang\} and Mok, \{Philip K.T.\}",

year = "2003",

month = oct,

doi = "10.1109/JSSC.2003.817256",

language = "English",

volume = "38",

pages = "1691--1702",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}

TY - JOUR

T1 - A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation

AU - Leung, Ka Nang

AU - Mok, Philip K.T.

PY - 2003/10

Y1 - 2003/10

N2 - A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-μm CMOS technology, and the active chip area is 568 μm × 541 μm. The total error of the output voltage due to line and load variations is less than ±0.25%, and the temperature coefficient is 38 ppm/°C. Moreover, the output voltage can recover within 2 μs for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 μV/√Hz, respectively.

AB - A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-μm CMOS technology, and the active chip area is 568 μm × 541 μm. The total error of the output voltage due to line and load variations is less than ±0.25%, and the temperature coefficient is 38 ppm/°C. Moreover, the output voltage can recover within 2 μs for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 μV/√Hz, respectively.

KW - CMOS voltage reference

KW - Capacitor-free low-dropout regulator (LDO)

KW - Damping-factor-control frequency compensation

KW - Loop-gain stability

UR - https://www.webofscience.com/wos/woscc/full-record/WOS:000185568500013

UR - https://openalex.org/W2034720635

UR - https://www.scopus.com/pages/publications/0141920411

U2 - 10.1109/JSSC.2003.817256

DO - 10.1109/JSSC.2003.817256

M3 - Journal Article

SN - 0018-9200

VL - 38

SP - 1691

EP - 1702

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 10

ER -

A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation

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Keywords

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