TY - GEN
T1 - A CMOS-compatible WORM memory for low-cost non-volatile memory applications
AU - Barsatan, Randy
AU - Man, Tsz Yin
AU - Chan, Mansun
PY - 2005
Y1 - 2005
N2 - A Write-Once-Read-Many (WORM) memory using a CMOS-compatible Antifuse (AF) element for low-cost nonvolatile memory is presented. The AF device is formed on an NMOS with PLDD implants (MOS-channel AF) to enhance hot-carrier effects. The AF is programmed by applying a high voltage across the channel until breakdown such that it becomes resistor. The devices were fabricated in standard TSMC 0.18μm process without any process modification. The channel breakdown was observed between 4.5V to 5V. The programmed resistance is in the kΩ range at miiliampere range of programming current. A 128-bit WORM architecture is presented based on an IO-select transistor and the AF memory cell. The architecture was designed and simulated in Cadence to verify the functionality of the device when formed in an array.
AB - A Write-Once-Read-Many (WORM) memory using a CMOS-compatible Antifuse (AF) element for low-cost nonvolatile memory is presented. The AF device is formed on an NMOS with PLDD implants (MOS-channel AF) to enhance hot-carrier effects. The AF is programmed by applying a high voltage across the channel until breakdown such that it becomes resistor. The devices were fabricated in standard TSMC 0.18μm process without any process modification. The channel breakdown was observed between 4.5V to 5V. The programmed resistance is in the kΩ range at miiliampere range of programming current. A 128-bit WORM architecture is presented based on an IO-select transistor and the AF memory cell. The architecture was designed and simulated in Cadence to verify the functionality of the device when formed in an array.
UR - https://openalex.org/W2547946391
UR - https://www.scopus.com/pages/publications/43549110690
U2 - 10.1109/EDSSC.2005.1635276
DO - 10.1109/EDSSC.2005.1635276
M3 - Conference Paper published in a book
SN - 0780393392
SN - 9780780393394
T3 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
SP - 339
EP - 342
BT - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Y2 - 19 December 2005 through 21 December 2005
ER -