TY - GEN
T1 - A CMOS monolithic implementation of a nonlinear element for arbitrary 1-D map generation
AU - Yuan, Jie
AU - Farhat, Nabil
AU - Van Der Spiegel, Jan
PY - 2006
Y1 - 2006
N2 - In a macroscopic approach, a single-chip cortical patch is designed based on the model of a bifurcating neuron. In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic clement is able to generate an arbitrary one-dimensional map with 12-bit resolution. The CMOS design employs a calibration scheme to maintain robustness against process variations. The element is fabricated in a 0.6μm CMOS process, and is driven under signals with IMHz frequency. It covers a die has an area of 0.2mm 2, and consumes 40mW power, with a 5V supply.
AB - In a macroscopic approach, a single-chip cortical patch is designed based on the model of a bifurcating neuron. In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic clement is able to generate an arbitrary one-dimensional map with 12-bit resolution. The CMOS design employs a calibration scheme to maintain robustness against process variations. The element is fabricated in a 0.6μm CMOS process, and is driven under signals with IMHz frequency. It covers a die has an area of 0.2mm 2, and consumes 40mW power, with a 5V supply.
UR - https://www.scopus.com/pages/publications/34547284197
M3 - Conference Paper published in a book
AN - SCOPUS:34547284197
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2765
EP - 2768
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -