A Dual-Path Bandwidth Extension Amplifier Topology with Dual-Loop Parallel Compensation

Hoi Lee; Ka Nang Leung; Philip K.T. Mok

doi:10.1109/JSSC.2003.817597

A Dual-Path Bandwidth Extension Amplifier Topology with Dual-Loop Parallel Compensation

Hoi Lee^*, Ka Nang Leung, Philip K.T. Mok

^*Corresponding author for this work

Department of Electronic and Computer Engineering

Research output: Contribution to journal › Journal Article › peer-review

69 Citations (Scopus)

Abstract

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-μm CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V/μs average slew rate while only dissipating 330 μW at 1.5 V, when driving a 25-kΩ//120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.

Original language	English
Pages (from-to)	1739-1744
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	38
Issue number	10
DOIs	https://doi.org/10.1109/JSSC.2003.817597
Publication status	Published - Oct 2003

Keywords

Amplifiers
Dual loop
Dual path
Frequency compensation
Multistage amplifiers

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10.1109/JSSC.2003.817597

Cite this

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title = "A Dual-Path Bandwidth Extension Amplifier Topology with Dual-Loop Parallel Compensation",

abstract = "A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-μm CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V/μs average slew rate while only dissipating 330 μW at 1.5 V, when driving a 25-kΩ//120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.",

keywords = "Amplifiers, Dual loop, Dual path, Frequency compensation, Multistage amplifiers",

author = "Hoi Lee and Leung, \{Ka Nang\} and Mok, \{Philip K.T.\}",

year = "2003",

month = oct,

doi = "10.1109/JSSC.2003.817597",

language = "English",

volume = "38",

pages = "1739--1744",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - A Dual-Path Bandwidth Extension Amplifier Topology with Dual-Loop Parallel Compensation

AU - Lee, Hoi

AU - Leung, Ka Nang

AU - Mok, Philip K.T.

PY - 2003/10

Y1 - 2003/10

N2 - A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-μm CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V/μs average slew rate while only dissipating 330 μW at 1.5 V, when driving a 25-kΩ//120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.

AB - A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-μm CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V/μs average slew rate while only dissipating 330 μW at 1.5 V, when driving a 25-kΩ//120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.

KW - Amplifiers

KW - Dual loop

KW - Dual path

KW - Frequency compensation

KW - Multistage amplifiers

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UR - https://openalex.org/W2014643058

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DO - 10.1109/JSSC.2003.817597

M3 - Journal Article

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JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 10

ER -

A Dual-Path Bandwidth Extension Amplifier Topology with Dual-Loop Parallel Compensation

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Keywords

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