A Dynamic Gate Driver IC with Automated Pattern Optimization for SiC Power MOSFETs

The switching transient of SiC power MOSFETs are often affected by the gate voltage (VGATE) swings due to the fast charging/discharging of their gate capacitances. Using a gate resistance (RG) can effectively limit the influx of gate current but reduces the switching speed of the transistor. Both factors can be improved using a dynamic gate driving scheme with varying RG. The optimum timings of the dynamic RG pattern are dependent on different SiC power MOSFETs and their operating conditions. Previously, a trial-and-error iterative process is required to determine the optimal timing. An automated method to optimize the timings of the dynamic RG pattern is proposed in this paper. The VGATE signal of the SiC power MOSFET is processed internally by an analog circuit and the resultant timing indicator (TSEG) is digitized for feedback through an on-chip TDC. The optimum dynamic gate drive timing TOPT is obtained by subtracting TSEG from the inherent delay cause by the sensing circuit. The output can be interpreted by an external compensator. A set of digital timing configurations are then fed back to the IC to optimize the dynamic RG pattern timings for the next switching cycle (TOPT(n+1)). The proposed dynamic gate drive IC can provide ringing suppression while maintaining high switching speed for SiC power MOSFETs automatically.