A fully-integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

C. Guo; C. W. Lo; Y. W. Choi; I. Hsu; T. Kan; D. Leung; A. Chan; H. C. Luong

A fully-integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

C. Guo^*, C. W. Lo, Y. W. Choi, I. Hsu, T. Kan, D. Leung, A. Chan, H. C. Luong

^*Corresponding author for this work

Department of Electronic and Computer Engineering

Research output: Contribution to conference › Conference Paper › peer-review

4 Citations (Scopus)

Abstract

A truly-monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully-integrated fractional-N synthesizer is presented. Implemented in standard 0.5-μm CMOS process and without any off-chip component, the receiver measures an image rejection of 79dB, sensitivity of -90dBm, IIP3 of -24dBm and NF of 22dB with power of 227mW and a chip area of 5.7mm². The synthesizer achieves a phase noise of -118dBc/Hz at 600kHz offset and settling time of less than 150μs.

Original language	English
Pages	241-244
Number of pages	4
Publication status	Published - 2001
Event	2001 VLSI Circuits Symposium - Kyoto, Japan Duration: 14 Jun 2001 → 16 Jun 2001

Conference

Conference	2001 VLSI Circuits Symposium
Country/Territory	Japan
City	Kyoto
Period	14/06/01 → 16/06/01

Cite this

@conference{dd00f9db41274579a9c52bb1182ba3a3,

title = "A fully-integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection",

abstract = "A truly-monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully-integrated fractional-N synthesizer is presented. Implemented in standard 0.5-μm CMOS process and without any off-chip component, the receiver measures an image rejection of 79dB, sensitivity of -90dBm, IIP3 of -24dBm and NF of 22dB with power of 227mW and a chip area of 5.7mm2. The synthesizer achieves a phase noise of -118dBc/Hz at 600kHz offset and settling time of less than 150μs.",

author = "C. Guo and Lo, \{C. W.\} and Choi, \{Y. W.\} and I. Hsu and T. Kan and D. Leung and A. Chan and Luong, \{H. C.\}",

year = "2001",

language = "English",

pages = "241--244",

note = "2001 VLSI Circuits Symposium ; Conference date: 14-06-2001 Through 16-06-2001",

}

TY - CONF

T1 - A fully-integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

AU - Guo, C.

AU - Lo, C. W.

AU - Choi, Y. W.

AU - Hsu, I.

AU - Kan, T.

AU - Leung, D.

AU - Chan, A.

AU - Luong, H. C.

PY - 2001

Y1 - 2001

N2 - A truly-monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully-integrated fractional-N synthesizer is presented. Implemented in standard 0.5-μm CMOS process and without any off-chip component, the receiver measures an image rejection of 79dB, sensitivity of -90dBm, IIP3 of -24dBm and NF of 22dB with power of 227mW and a chip area of 5.7mm2. The synthesizer achieves a phase noise of -118dBc/Hz at 600kHz offset and settling time of less than 150μs.

AB - A truly-monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully-integrated fractional-N synthesizer is presented. Implemented in standard 0.5-μm CMOS process and without any off-chip component, the receiver measures an image rejection of 79dB, sensitivity of -90dBm, IIP3 of -24dBm and NF of 22dB with power of 227mW and a chip area of 5.7mm2. The synthesizer achieves a phase noise of -118dBc/Hz at 600kHz offset and settling time of less than 150μs.

UR - https://www.scopus.com/pages/publications/0034784824

M3 - Conference Paper

AN - SCOPUS:0034784824

SP - 241

EP - 244

T2 - 2001 VLSI Circuits Symposium

Y2 - 14 June 2001 through 16 June 2001

ER -

A fully-integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

Abstract

Conference

Other files and links

Fingerprint

Cite this