A HYBRID STRUCTURE-BASED SEMANTIC SEGMENTATION METHOD FOR INDUSTRIAL MEASUREMENT OF FORM AND POSITION TOLERANCE ON CHIP SOCKETS

A chip socket is a mechanical and electrical system that establishes reliable electronic interconnection paths between the chip and the test board to facilitate signal transmission. Form and positional tolerance control is key to determining the quality of the chip socket. When faced with highly precise CPU chip sockets containing thousands of contacts distributed over a very small area, current technologies still struggle to meet the demands for high-precision, rapid, and real-time measurements simultaneously. This presents a significant challenge to process stability and product quality. To address this issue, a hybrid model of tandem structure stitching (HTSS) is proposed to effectively and efficiently measure the form and position tolerance of CPU chip sockets. The front-end model is a improved BiSeNet (IMP-BiSeNet) semantic segmentation network, which improves the convolutional module by incorporating a self-attention mechanism. Meanwhile, a structural reparameterization in the style of RepVGG is designed to separate the architectures used during training and inference, thereby reducing the training time and inference time. Furthermore, the overlay maps extracted from the modified BiSeNet network are inputted into the OTSU model for additional processing. The chip contact form and positional tolerance are then obtained through target size and position calculation. The accuracy of the HTSS model is validated through tolerance inspection experiments conducted on a robotic vision measurement system. The results show that IMP-BiSeNet improves the mIoU by 5.69% compared to BiSeNet. All the measured tolerance values are less than 0.1 mm, which meets the tolerance requirements. The model offers an effective and efficient approach to enhancing the accuracy of tolerance measurement for precision devices.