Abstract
The complexity of Finite Impulse Response (FIR) Alters is dominated by the number of adders (subtractors) used to implement the coefficient multipliers. It is well known that Common Subexpression Elimination (CSE) method based on Canonic Signed Digit (CSD) representation considerably reduces the number of adders in coefficient multipliers. Recently, a binary based CSE (BSE) technique was proposed, which produced better reduction of adders compared to the CSD based CSE. In this paper, we propose a new 4-bit Binary based CSE (BCSE) method which employs 4-bit Common Subexpressions (CSs). Design examples show an average adder reduction of 31.2 % over the conventional CSD based CSE and 15% reduction over BSE.
| Original language | English |
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| Article number | 4253141 |
| Pages (from-to) | 2327-2330 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| DOIs | |
| Publication status | Published - 2007 |
| Externally published | Yes |
| Event | 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: 27 May 2007 → 30 May 2007 |