A new distributed congestion control mechanism for networks on chip

Congestion is an important issue in networks and significantly affects network performance. Various congestion control mechanisms have been proposed for the Internet, interconnection networks, etc. However, they are not suitable for network-on-chip systems. Based on the requirements of chip designs, we propose a new distributed congestion control mechanism for network-on-chip systems in this paper. The mechanism uses a new detection metric, the length of the occupied source buffer, to detect network congestion. The new metric is more accurate compared with others. Using the new metric, the congestion information can be directly obtained inside a node. This allows the mechanism to be fully distributed and without requiring any global information. In addition, the presence of real time traffic is considered. Throttling is not required for such traffic to provide QoS. An asymmetric router architecture with additional congestion control unit is also proposed to facilitate the implementation of the new congestion control mechanism. The overhead is relatively low, about 1.79% overhead in area and 2.06 mW in power consumption. The simulations are carried out in OPNET. The results show that our congestion control mechanism alleviates performance degradation for loads beyond saturation, and maintains adequate levels of throughput at higher loads. The new mechanism achieves better network performance than others under different traffic patterns and network sizes.