TY - GEN
T1 - A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability
AU - Salahuddin, Shairfemuhammad
AU - Jiao, Hailong
AU - Kursun, Volkan
PY - 2013
Y1 - 2013
N2 - A new FinFET memory circuit technique based on asymmetrically gate underlap engineered bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline access transistors are weakened during read operations while enhanced during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability and write ability are both enhanced by up to 6.12x and 58%, respectively, without causing any area overhead as compared to the standard symmetrical six-FinFET SRAM cells in a 15nm FinFET technology. The leakage power consumption is also reduced by up to 96.5% with the proposed asymmetrical FinFET SRAM cell as compared to the standard six-FinFET SRAM cells with symmetrical bitline access transistors.
AB - A new FinFET memory circuit technique based on asymmetrically gate underlap engineered bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline access transistors are weakened during read operations while enhanced during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability and write ability are both enhanced by up to 6.12x and 58%, respectively, without causing any area overhead as compared to the standard symmetrical six-FinFET SRAM cells in a 15nm FinFET technology. The leakage power consumption is also reduced by up to 96.5% with the proposed asymmetrical FinFET SRAM cell as compared to the standard six-FinFET SRAM cells with symmetrical bitline access transistors.
KW - asymmetrical gate underlap engineering
KW - data stability
KW - leakage power consumption
KW - Memory
KW - on-die cache
KW - static noise margin
KW - write margin
UR - https://www.scopus.com/pages/publications/84879574589
U2 - 10.1109/ISQED.2013.6523634
DO - 10.1109/ISQED.2013.6523634
M3 - Conference Paper published in a book
AN - SCOPUS:84879574589
SN - 9781467349536
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 353
EP - 358
BT - Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013
T2 - 14th International Symposium on Quality Electronic Design, ISQED 2013
Y2 - 4 March 2013 through 6 March 2013
ER -