A partial enhanced-scan approach to robust delay-fault test generation for sequential circuits

The authors address the problem of robust path-delay-fault test generation for sequential circuits by using a partial enhanced-scan/standard-scan approach and by using the notion of scan shifting. Vector pairs that can be obtained by single-bit shifts can be applied at speed under standard scan. An algorithm is given to determine an efficient ordering of the flip-flops in the scan chain using the information derived from running a delay test generator on the circuit. Given an ordering of the flip-flops, the authors give an optimization algorithm that attempts to minimize the number of flip-flops to be made enhanced-scan so as to obtain the required level of delay-fault coverage.