A Physical Poly-Silicon Thin Film Transistors Model for Circuit Simulations

Chester C. Li; Hiroyuki Ikeda; Takahide Inoue; Ping K. Ko

A Physical Poly-Silicon Thin Film Transistors Model for Circuit Simulations

Chester C. Li, Hiroyuki Ikeda^*, Takahide Inoue, Ping K. Ko

^*Corresponding author for this work

Research output: Contribution to journal › Conference article published in journal › peer-review

14 Citations (Scopus)

Abstract

This paper presents a poly-silicon thin film transistors model for circuit simulations. The drain current model includes the effects of hot carrier, drain induced barrier lowering (DLBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is lightly linked to the drain current and its derivatives. This model has been implemented in SPICE. Simulation and experimental results are compared.

Original language	English
Pages (from-to)	497-500
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting, IEDM
Publication status	Published - 1993
Externally published	Yes
Event	Proceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA Duration: 5 Dec 1993 → 8 Dec 1993

Bibliographical note

Publisher Copyright:
© 1993 IEEE.

Cite this

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title = "A Physical Poly-Silicon Thin Film Transistors Model for Circuit Simulations",

abstract = "This paper presents a poly-silicon thin film transistors model for circuit simulations. The drain current model includes the effects of hot carrier, drain induced barrier lowering (DLBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is lightly linked to the drain current and its derivatives. This model has been implemented in SPICE. Simulation and experimental results are compared.",

author = "Li, \{Chester C.\} and Hiroyuki Ikeda and Takahide Inoue and Ko, \{Ping K.\}",

note = "Publisher Copyright: {\textcopyright} 1993 IEEE.; Proceedings of the 1993 IEEE International Electron Devices Meeting ; Conference date: 05-12-1993 Through 08-12-1993",

year = "1993",

language = "English",

pages = "497--500",

journal = "Technical Digest - International Electron Devices Meeting, IEDM",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - A Physical Poly-Silicon Thin Film Transistors Model for Circuit Simulations

AU - Li, Chester C.

AU - Ikeda, Hiroyuki

AU - Inoue, Takahide

AU - Ko, Ping K.

PY - 1993

Y1 - 1993

N2 - This paper presents a poly-silicon thin film transistors model for circuit simulations. The drain current model includes the effects of hot carrier, drain induced barrier lowering (DLBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is lightly linked to the drain current and its derivatives. This model has been implemented in SPICE. Simulation and experimental results are compared.

AB - This paper presents a poly-silicon thin film transistors model for circuit simulations. The drain current model includes the effects of hot carrier, drain induced barrier lowering (DLBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is lightly linked to the drain current and its derivatives. This model has been implemented in SPICE. Simulation and experimental results are compared.

UR - https://www.scopus.com/pages/publications/0027880069

M3 - Conference article published in journal

AN - SCOPUS:0027880069

SN - 0163-1918

SP - 497

EP - 500

JO - Technical Digest - International Electron Devices Meeting, IEDM

JF - Technical Digest - International Electron Devices Meeting, IEDM

T2 - Proceedings of the 1993 IEEE International Electron Devices Meeting

Y2 - 5 December 1993 through 8 December 1993

ER -

A Physical Poly-Silicon Thin Film Transistors Model for Circuit Simulations

Abstract

Bibliographical note

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