TY - GEN
T1 - A reconfigurable multi-stage frequency response masking filter bank architecture for software defined radio receivers
AU - Smitha, K. G.
AU - Mahesh, R.
AU - Vinod, A. P.
PY - 2008
Y1 - 2008
N2 - The most computationally demanding part in the digital front-end of a Software radio receiver is the channelizer, which operates at the highest sampling rate. The channelizer extracts multiple narrowband channels from the digitized wideband input signal. The limitation of the conventional uniform Discrete Fourier transform (DFT) filter bank channelizer is that, it is incapable of extracting channels of multiple bandwidths, as the prototype filter has fixed equal bandwidths. Reconfigurable filter bank architecture for the SDR channelizer, based on multi-stage frequency response masking technique is proposed in this paper. The proposed architecture is capable of extracting channels with different bandwidths corresponding to different wireless communication standards. Design examples show that proposed architecture offers a complexity reduction of 97.2 % over the conventional Per-Channel (PC) approach and DFT filter banks.
AB - The most computationally demanding part in the digital front-end of a Software radio receiver is the channelizer, which operates at the highest sampling rate. The channelizer extracts multiple narrowband channels from the digitized wideband input signal. The limitation of the conventional uniform Discrete Fourier transform (DFT) filter bank channelizer is that, it is incapable of extracting channels of multiple bandwidths, as the prototype filter has fixed equal bandwidths. Reconfigurable filter bank architecture for the SDR channelizer, based on multi-stage frequency response masking technique is proposed in this paper. The proposed architecture is capable of extracting channels with different bandwidths corresponding to different wireless communication standards. Design examples show that proposed architecture offers a complexity reduction of 97.2 % over the conventional Per-Channel (PC) approach and DFT filter banks.
UR - https://www.scopus.com/pages/publications/51749106818
U2 - 10.1109/ISCAS.2008.4541360
DO - 10.1109/ISCAS.2008.4541360
M3 - Conference Paper published in a book
AN - SCOPUS:51749106818
SN - 9781424416844
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 85
EP - 88
BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Y2 - 18 May 2008 through 21 May 2008
ER -