A resistor/transconductor network for linear fitting

Bertram E. Shi; Lina Gao; Kwok Kit Lau

doi:10.1109/82.839668

A resistor/transconductor network for linear fitting

Bertram E. Shi^*, Lina Gao, Kwok Kit Lau

^*Corresponding author for this work

HKUST Fok Ying Tung Graduate School

Research output: Contribution to journal › Journal Article › peer-review

2 Citations (Scopus)

Abstract

We present a continuous time analog VLSI CMOS circuit consisting of resistors and transconductors for computing the best-fit line to a set of data points. The circuit can implement standard least-squares linear fitting, as well as a form of linear fitting that is more robust to outliers. We analyze the static and transient response of the chip, and present design criteria given desired constraints on speed and accuracy. Finally, we describe the transistor level design and measurement results from a 50-input prototype fabricated using a 1.2 //m n-well process.

Original language	English
Pages (from-to)	322-331
Number of pages	10
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	47
Issue number	4
DOIs	https://doi.org/10.1109/82.839668
Publication status	Published - Apr 2000

Keywords

Cmos analog integrated circuits
Least-squares methods
Linear fitting
Parallel architecture
Robust statistics

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10.1109/82.839668

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abstract = "We present a continuous time analog VLSI CMOS circuit consisting of resistors and transconductors for computing the best-fit line to a set of data points. The circuit can implement standard least-squares linear fitting, as well as a form of linear fitting that is more robust to outliers. We analyze the static and transient response of the chip, and present design criteria given desired constraints on speed and accuracy. Finally, we describe the transistor level design and measurement results from a 50-input prototype fabricated using a 1.2 //m n-well process.",

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AU - Shi, Bertram E.

AU - Gao, Lina

AU - Lau, Kwok Kit

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N2 - We present a continuous time analog VLSI CMOS circuit consisting of resistors and transconductors for computing the best-fit line to a set of data points. The circuit can implement standard least-squares linear fitting, as well as a form of linear fitting that is more robust to outliers. We analyze the static and transient response of the chip, and present design criteria given desired constraints on speed and accuracy. Finally, we describe the transistor level design and measurement results from a 50-input prototype fabricated using a 1.2 //m n-well process.

AB - We present a continuous time analog VLSI CMOS circuit consisting of resistors and transconductors for computing the best-fit line to a set of data points. The circuit can implement standard least-squares linear fitting, as well as a form of linear fitting that is more robust to outliers. We analyze the static and transient response of the chip, and present design criteria given desired constraints on speed and accuracy. Finally, we describe the transistor level design and measurement results from a 50-input prototype fabricated using a 1.2 //m n-well process.

KW - Cmos analog integrated circuits

KW - Least-squares methods

KW - Linear fitting

KW - Parallel architecture

KW - Robust statistics

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JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

IS - 4

ER -

A resistor/transconductor network for linear fitting

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Keywords

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