A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis

Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, traditional accurate power simulation requires time-consuming back-end processing and simulation steps, which significantly impede design optimization. To address this, we propose ATLAS, which can predict the ultimate time-based layout power for any new design in the gate-level netlist. In addition, we extend ATLAS to support power prediction using only RTL-stage toggle information, further increasing its applicability and efficiency. To the best of our knowledge, ATLAS is the first work that supports both time-based power simulation and general cross-design power modeling. It achieves such general time-based power modeling by proposing a new pre-training and fine-tuning paradigm customized for circuit power. Targeting golden per-cycle layout power from commercial tools, our ATLAS achieves the average mean absolute percentage error (MAPE) of only 5.41%, 3.79%, and 7.51% for the clock tree, register, and combinational power groups, respectively, without any layout information. Overall, the average MAPE for the total power of the entire design is 3.05%, and the inference speed of a workload is significantly faster than the standard flow of commercial tools. Furthermore, ATLAS can bypass the time-consuming signal propagation process, and when using only RTL-stage toggle information, achieves a total power MAPE as low as 5.00%.