Abstract
A simple method is proposed to grow thermal SiO2 interlayer when performing solid-phase-crystallized (SPC) process. By employing such interlayer between SPC polycrystalline silicon channel and Al2O3 gate dielectric, highperformance SPC thin-film transistors (TFTs) with field effect mobility of 67.80 cm2V s-1 and ON/OFF ratio of 2.31 × 108 at Vds =-0.1 V are achieved due to the superior interface quality and improved grain boundaries by the incorporation of excess Si interstitials. The TFT with interlayer also exhibits good reliability under negative bias temperature stress test.
| Original language | English |
|---|---|
| Article number | 6762850 |
| Pages (from-to) | 548-550 |
| Number of pages | 3 |
| Journal | IEEE Electron Device Letters |
| Volume | 35 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 1 May 2014 |
Keywords
- Solid-phase-crystallized
- interlayer.
- polycrystalline silicon
- thin-film transistor
Fingerprint
Dive into the research topics of 'A Simple method to grow thermal SiO2 interlayer for high-performance SPC poly-Si TFTs using Al2O3 gate dielectric'. Together they form a unique fingerprint.Cite this
- APA
- Author
- BIBTEX
- Harvard
- Standard
- RIS
- Vancouver