A Single-Controller-Four-Output Digital LDO With Priority-Time-Multiplexing Scheme and Clamping Loops in 65-nm CMOS

This brief presents an improved single-controller-multiple-output (SCMO) digital LDO regulating four separate outputs with only one digital controller. The shared digital controller employs a priority-time-multiplexing scheme for optimal performance. The area of the digital controller is reduced by 25% compared to the sum of four separate controllers. Dead-zone control is utilized to save quiescent power during steady state. Two 2-level comparators are employed to generate a 4-bit signal with minimum quiescent current. Clamping loops are also implemented to reduce the undershoot/overshoot. This SCMO digital LDO is verified in a 65-nm CMOS process. There is no cross regulation, and the proposed priority-time-multiplexing scheme ensures an efficient assignment of clock cycles to the most needed output.