A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs

Arish Sateesan; Sharad Sinha; Smitha K. G; A. P. Vinod

doi:10.1007/s11063-021-10458-1

A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs

Arish Sateesan^*, Sharad Sinha, Smitha K. G, A. P. Vinod

^*Corresponding author for this work

Research output: Contribution to journal › Review article › peer-review

17 Citations (Scopus)

Abstract

In today’s world, the applications of convolutional neural networks (CNN) are limitless and are employed in numerous fields. The CNNs get wider and deeper to achieve near-human accuracy. Implementing such networks on resource constrained hardware is a cumbersome task. CNNs need to be optimized both on hardware and algorithmic levels to compress and fit into resource limited devices. This survey aims to investigate different optimization techniques of Vision CNNs, both on algorithmic and hardware level, which would help in efficient hardware implementation, especially for FPGAs.

Original language	English
Pages (from-to)	2331-2377
Number of pages	47
Journal	Neural Processing Letters
Volume	53
Issue number	3
DOIs	https://doi.org/10.1007/s11063-021-10458-1
Publication status	Published - Jun 2021
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature.

Keywords

Convolutional Neural Networks
FPGA
Hardware Optimization
Resource Constrained Hardware

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10.1007/s11063-021-10458-1

Cite this

@article{a7e6e930ac914d46905e6650971199e3,

title = "A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs",

abstract = "In today{\textquoteright}s world, the applications of convolutional neural networks (CNN) are limitless and are employed in numerous fields. The CNNs get wider and deeper to achieve near-human accuracy. Implementing such networks on resource constrained hardware is a cumbersome task. CNNs need to be optimized both on hardware and algorithmic levels to compress and fit into resource limited devices. This survey aims to investigate different optimization techniques of Vision CNNs, both on algorithmic and hardware level, which would help in efficient hardware implementation, especially for FPGAs.",

keywords = "Convolutional Neural Networks, FPGA, Hardware Optimization, Resource Constrained Hardware",

author = "Arish Sateesan and Sharad Sinha and \{K. G\}, Smitha and Vinod, \{A. P.\}",

note = "Publisher Copyright: {\textcopyright} 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature.",

year = "2021",

month = jun,

doi = "10.1007/s11063-021-10458-1",

language = "English",

volume = "53",

pages = "2331--2377",

journal = "Neural Processing Letters",

issn = "1370-4621",

publisher = "Springer Netherlands",

number = "3",

}

TY - JOUR

T1 - A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs

AU - Sateesan, Arish

AU - Sinha, Sharad

AU - K. G, Smitha

AU - Vinod, A. P.

PY - 2021/6

Y1 - 2021/6

N2 - In today’s world, the applications of convolutional neural networks (CNN) are limitless and are employed in numerous fields. The CNNs get wider and deeper to achieve near-human accuracy. Implementing such networks on resource constrained hardware is a cumbersome task. CNNs need to be optimized both on hardware and algorithmic levels to compress and fit into resource limited devices. This survey aims to investigate different optimization techniques of Vision CNNs, both on algorithmic and hardware level, which would help in efficient hardware implementation, especially for FPGAs.

AB - In today’s world, the applications of convolutional neural networks (CNN) are limitless and are employed in numerous fields. The CNNs get wider and deeper to achieve near-human accuracy. Implementing such networks on resource constrained hardware is a cumbersome task. CNNs need to be optimized both on hardware and algorithmic levels to compress and fit into resource limited devices. This survey aims to investigate different optimization techniques of Vision CNNs, both on algorithmic and hardware level, which would help in efficient hardware implementation, especially for FPGAs.

KW - Convolutional Neural Networks

KW - FPGA

KW - Hardware Optimization

KW - Resource Constrained Hardware

UR - https://www.webofscience.com/wos/woscc/full-record/WOS:000636913400001

UR - https://openalex.org/W3140770201

UR - https://www.scopus.com/pages/publications/85103636526

U2 - 10.1007/s11063-021-10458-1

DO - 10.1007/s11063-021-10458-1

M3 - Review article

SN - 1370-4621

VL - 53

SP - 2331

EP - 2377

JO - Neural Processing Letters

JF - Neural Processing Letters

IS - 3

ER -

A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs

Abstract

Bibliographical note

Keywords

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