A voltage-scalable zero-delay-overhead scheme for standby power reduction in dynamic register files

A voltage-scalable bitline leakage current suppression technique with zero wake-up delay penalty is proposed to minimize the standby power consumption of low threshold voltage dynamic register files (RFs). Leakage currents via the pull-down paths of a wide fan-in dynamic logic gate are suppressed with a combination of fine-grained power gating and voltage lowering. A leakage-biased write bitline tracks the stored data configuration in a column in order to minimize write bitline leakage currents. At 1.2V, leakage power savings of up to 44.3% are achieved in a 4Kib 1-read/1-write-port RF by incurring a 3.2% penalty in read access frequency. Active power overheads for consecutive reads and writes are 7.3% and 5.6% respectively.