Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology

Luis Chen; C. Patrick Yue

doi:10.1109/VDAT.2008.4542458

Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology

Luis Chen^*, C. Patrick Yue

^*Corresponding author for this work

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

Abstract

A self-biased, V_TH tracking current reference circuit is designed in 90nm CMOS process. A finite state machine automatically adjusts the reference current to achieve ±5% deviation across process variation. The bias circuit is used on a differential test circuit and simulation shows a maximum of 8.53% variation in bias current.

Original language	English
Title of host publication	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages	243-246
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2008.4542458
Publication status	Published - 2008
Externally published	Yes
Event	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan, Province of China Duration: 23 Apr 2008 → 25 Apr 2008

Publication series

Name	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	23/04/08 → 25/04/08

Access to Document

10.1109/VDAT.2008.4542458

Cite this

@inproceedings{7e840d6aae664392a97a25a29245f943,

title = "Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology",

abstract = "A self-biased, VTH tracking current reference circuit is designed in 90nm CMOS process. A finite state machine automatically adjusts the reference current to achieve ±5\% deviation across process variation. The bias circuit is used on a differential test circuit and simulation shows a maximum of 8.53\% variation in bias current.",

author = "Luis Chen and Yue, \{C. Patrick\}",

year = "2008",

doi = "10.1109/VDAT.2008.4542458",

language = "English",

isbn = "9781424416172",

series = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT",

pages = "243--246",

booktitle = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT",

note = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT ; Conference date: 23-04-2008 Through 25-04-2008",

}

Chen, L & Yue, CP 2008, Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology. in 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT., 4542458, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, pp. 243-246, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, Hsinchu, Taiwan, Province of China, 23/04/08. https://doi.org/10.1109/VDAT.2008.4542458

Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology. / Chen, Luis; Yue, C. Patrick.
2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 243-246 4542458 (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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AU - Chen, Luis

AU - Yue, C. Patrick

PY - 2008

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N2 - A self-biased, VTH tracking current reference circuit is designed in 90nm CMOS process. A finite state machine automatically adjusts the reference current to achieve ±5% deviation across process variation. The bias circuit is used on a differential test circuit and simulation shows a maximum of 8.53% variation in bias current.

AB - A self-biased, VTH tracking current reference circuit is designed in 90nm CMOS process. A finite state machine automatically adjusts the reference current to achieve ±5% deviation across process variation. The bias circuit is used on a differential test circuit and simulation shows a maximum of 8.53% variation in bias current.

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UR - https://openalex.org/W2119999726

UR - https://www.scopus.com/pages/publications/50649124720

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M3 - Conference Paper published in a book

SN - 9781424416172

T3 - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

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EP - 246

BT - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

T2 - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Y2 - 23 April 2008 through 25 April 2008

ER -

Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology

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