Abstract
This paper presents a novel hybrid finite-domain constraint solving engine for RTL circuits. We describe how DPLL search is modified for search in combined integer and Boolean domains by using efficient finite-domain constraint propagation. This enables efficient combination of Boolean SAT and linear integer arithmetic solving techniques. We automatically use control and data-path abstraction in RTL descriptions. We use conflict-based learning using the variables on the boundary of control and data-path for additional performance benefits. Finally, we analyze the hybrid constraint solver experimentally using some example circuits.
| Original language | English |
|---|---|
| Pages (from-to) | 212-217 |
| Number of pages | 6 |
| Journal | Proceedings - Design Automation Conference |
| DOIs | |
| Publication status | Published - 2004 |
| Externally published | Yes |
| Event | Proceedings of the 41st Design Automation Conference - San Diego, CA, United States Duration: 7 Jun 2004 → 11 Jun 2004 |
Keywords
- Bit-vector arithmetic
- Boolean Satisfiability
- Decision Procedures
- Design Verification
- Integer Linear Programming