An efficient finite-domain constraint solver for circuits

G. Parthasarathy*, M. K. Iyer, K. T. Cheng, Li C. Wang

*Corresponding author for this work

Research output: Contribution to journalConference article published in journalpeer-review

30 Citations (Scopus)

Abstract

This paper presents a novel hybrid finite-domain constraint solving engine for RTL circuits. We describe how DPLL search is modified for search in combined integer and Boolean domains by using efficient finite-domain constraint propagation. This enables efficient combination of Boolean SAT and linear integer arithmetic solving techniques. We automatically use control and data-path abstraction in RTL descriptions. We use conflict-based learning using the variables on the boundary of control and data-path for additional performance benefits. Finally, we analyze the hybrid constraint solver experimentally using some example circuits.

Original languageEnglish
Pages (from-to)212-217
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
Publication statusPublished - 2004
Externally publishedYes
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: 7 Jun 200411 Jun 2004

Keywords

  • Bit-vector arithmetic
  • Boolean Satisfiability
  • Decision Procedures
  • Design Verification
  • Integer Linear Programming

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