Abstract
An improved recycling folded cascode operational transconductance amplifier with gain boosting and enhanced phase-margin is proposed. Among four variants of folded cascode amplifiers that have been implemented in TSMC 0.18μm CMOS process under same power and area constraints, the proposed amplifier achieves the lowest settling error of less than 0.5% compared to 1.1% settling error by Improved Recycling Folded Cascode (IRFC), 1.4% settling error by Recycling Folded Cascode (RFC) and 30% settling error by conventional Folded Cascode (FC) amplifier. This performance enhancement is attributed to 30dB increment in low-frequency gain and 7° improvement in the phase margin when compared with the second best performing Improved Recycling Folded Cascode amplifier.
| Original language | English |
|---|---|
| Title of host publication | 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 2473-2476 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781479983919 |
| DOIs | |
| Publication status | Published - 27 Jul 2015 |
| Externally published | Yes |
| Event | IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 24 May 2015 → 27 May 2015 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Volume | 2015-July |
| ISSN (Print) | 0271-4310 |
Conference
| Conference | IEEE International Symposium on Circuits and Systems, ISCAS 2015 |
|---|---|
| Country/Territory | Portugal |
| City | Lisbon |
| Period | 24/05/15 → 27/05/15 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
Keywords
- Gain boosting
- Improved recycling folded cascode amplifier
- phase margin enhancement
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