Arbiter designs for multiprocessor interconnection networks

Interconnection networks (ins) play an important role in Multiprocessor systems. Arbiters are required to resolve memory access conflicts and path conflicts in the ins. The paper presents implementation of these arbiters considering both equal acceptance and priority to infrequent or i/o requests. Introduction of self-checking circuits to improve the reliability has also been considered. The ins considered are crossbar, multistage interconnection networks and multiple-bus.