ASAP: Accurate Synthesis Analysis and Prediction with Multi-Task Learning

With the ever-growing scale of circuits, the design time also increases dramatically and hinders an efficient chip development process. One way to accelerate the chip design process is to equip designers with early estimations of the circuit metrics without actually running the time-consuming circuit implementation flow. In this paper, we propose a methodology for accurate synthesis results prediction based on deep neural networks. More specifically, reckoning the relevance of circuit metrics during synthesis, we propose to use multi-task learning (MTL) to simultaneously predict circuit delay and area after logic synthesis, given the hardware description language design and the synthesis configuration sequence. A multi-head attention mechanism is developed to allow knowledge sharing between the predictions for delay and area to improve the model performance. Experimental results on 780,000 data points show that the testing mean-absolute-percentage-error (MAPE) on unseen designs can achieve 6%, which is about 3× lower than existing studies. Moreover, we demonstrate that the proposed MTL model can facilitate circuit design space exploration, which can effectively obtain superior designs in terms of area and delay.