Boolean behavior extraction from circuit layout

A Boolean behavior extraction method for static MOS circuits is proposed. From the signal-flow point of view, this approach can unify the functionality extraction for different design styles, including pass transistor logic, which cannot be treated using the traditional gate-level circuit model. To handle high-impedance states in MOS transistors, three Boolean equations, which are an extension of two-valued Boolean equations, are needed to describe the behavior of each node. Rules are presented to extract the Boolean behavior as well as to check the electrical safeness at some special nodes. An algorithm is used to identify these special nodes and guide the rules to perform functionality extraction. The extraction process is fast, since rules only apply to a small portion of the transistor group each time and few signal paths need to be found. Furthermore, it is easy to locate design error, both electrical and functional, because the error is confined to a small region by the algorithm during the extraction phase.