Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections

Jiachen Jiang; Yanan Sun; Weifeng He; Zhigang Mao; Volkan Kursun

doi:10.1109/ASICON47005.2019.8983463

Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections

Jiachen Jiang, Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun

Department of Electronic and Computer Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

1 Citation (Scopus)

Abstract

In this paper, a robust monolithic three-dimensional (M3D) 4N4P eight carbon nanotube MOSFETs (8-CN-MOSFET) static random-access memory (SRAM) cell is presented for achieving high integration density with tolerance to the removal of metallic carbon nanotubes. While maintaining the high functional yield and robust read/write operations, the layout area of the proposed 16K-bit M3D 4N4P 8-CN-MOSFET SRAM array is reduced by 45.32% and 31.56% as compared to the previously published 2D and M3D 6N2P 8-CN-MOSFET SRAM circuits, respectively.

Original language	English
Title of host publication	Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019
Editors	Fan Ye, Ting-Ao Tang
Publisher	IEEE Computer Society
ISBN (Electronic)	9781728107356
DOIs	https://doi.org/10.1109/ASICON47005.2019.8983463
Publication status	Published - Oct 2019
Event	13th IEEE International Conference on ASIC, ASICON 2019 - Chongqing, China Duration: 29 Oct 2019 → 1 Nov 2019

Publication series

Name	Proceedings of International Conference on ASIC
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Conference

Conference	13th IEEE International Conference on ASIC, ASICON 2019
Country/Territory	China
City	Chongqing
Period	29/10/19 → 1/11/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

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10.1109/ASICON47005.2019.8983463

Cite this

Jiang, J., Sun, Y., He, W., Mao, Z., & Kursun, V. (2019). Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections. In F. Ye, & T.-A. Tang (Eds.), Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019 Article 8983463 (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASICON47005.2019.8983463

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title = "Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections",

abstract = "In this paper, a robust monolithic three-dimensional (M3D) 4N4P eight carbon nanotube MOSFETs (8-CN-MOSFET) static random-access memory (SRAM) cell is presented for achieving high integration density with tolerance to the removal of metallic carbon nanotubes. While maintaining the high functional yield and robust read/write operations, the layout area of the proposed 16K-bit M3D 4N4P 8-CN-MOSFET SRAM array is reduced by 45.32\% and 31.56\% as compared to the previously published 2D and M3D 6N2P 8-CN-MOSFET SRAM circuits, respectively.",

author = "Jiachen Jiang and Yanan Sun and Weifeng He and Zhigang Mao and Volkan Kursun",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 13th IEEE International Conference on ASIC, ASICON 2019 ; Conference date: 29-10-2019 Through 01-11-2019",

year = "2019",

month = oct,

doi = "10.1109/ASICON47005.2019.8983463",

language = "English",

series = "Proceedings of International Conference on ASIC",

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editor = "Fan Ye and Ting-Ao Tang",

booktitle = "Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019",

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Jiang, J, Sun, Y, He, W, Mao, Z & Kursun, V 2019, Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections. in F Ye & T-A Tang (eds), Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019., 8983463, Proceedings of International Conference on ASIC, IEEE Computer Society, 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, 29/10/19. https://doi.org/10.1109/ASICON47005.2019.8983463

Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections. / Jiang, Jiachen; Sun, Yanan; He, Weifeng et al.
Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019. ed. / Fan Ye; Ting-Ao Tang. IEEE Computer Society, 2019. 8983463 (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections

AU - Jiang, Jiachen

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AU - Mao, Zhigang

AU - Kursun, Volkan

PY - 2019/10

Y1 - 2019/10

N2 - In this paper, a robust monolithic three-dimensional (M3D) 4N4P eight carbon nanotube MOSFETs (8-CN-MOSFET) static random-access memory (SRAM) cell is presented for achieving high integration density with tolerance to the removal of metallic carbon nanotubes. While maintaining the high functional yield and robust read/write operations, the layout area of the proposed 16K-bit M3D 4N4P 8-CN-MOSFET SRAM array is reduced by 45.32% and 31.56% as compared to the previously published 2D and M3D 6N2P 8-CN-MOSFET SRAM circuits, respectively.

AB - In this paper, a robust monolithic three-dimensional (M3D) 4N4P eight carbon nanotube MOSFETs (8-CN-MOSFET) static random-access memory (SRAM) cell is presented for achieving high integration density with tolerance to the removal of metallic carbon nanotubes. While maintaining the high functional yield and robust read/write operations, the layout area of the proposed 16K-bit M3D 4N4P 8-CN-MOSFET SRAM array is reduced by 45.32% and 31.56% as compared to the previously published 2D and M3D 6N2P 8-CN-MOSFET SRAM circuits, respectively.

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DO - 10.1109/ASICON47005.2019.8983463

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T3 - Proceedings of International Conference on ASIC

BT - Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019

A2 - Ye, Fan

A2 - Tang, Ting-Ao

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T2 - 13th IEEE International Conference on ASIC, ASICON 2019

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Jiang J, Sun Y, He W, Mao Z, Kursun V. Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections. In Ye F, Tang TA, editors, Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019. IEEE Computer Society. 2019. 8983463. (Proceedings of International Conference on ASIC). doi: 10.1109/ASICON47005.2019.8983463

Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections

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