Characterization of edge direct tunneling leakage of gate misaligned double gate MOSFETs

In this paper, the edge-direct-tunneling of gate-misaligned double-gate SOI MOSFETs was characterized. Gate misalignment produces gate overlap at heavily-doped source or drain region, which will introduce significant edge-direct-tunneling current. The tunneling current increases quickly with the increase of gate misalignment value, and it is asymmetric to source and drain. At same gate misalignment value, the inverter or inverter-chain consists of double-gate SOI MOSFETs with bottom gate shift to drain side has twice the gate current than that with bottom gate shift to source side.