Correction to “Power Estimation Methods for Sequential Logic Circuits” (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1995) 3(3) (404–416) (10.1109/92.406998))

Chi Ying Tsui; José Monteiro; Massoud Pedram; Srinivas Devadas; Alvin M. Despain; Bill Lin

doi:10.1109/TVLSI.1996.544414

Correction to “Power Estimation Methods for Sequential Logic Circuits” (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1995) 3(3) (404–416) (10.1109/92.406998))

Chi Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin

Department of Electronic and Computer Engineering

Research output: Contribution to journal › Comment/debate

Abstract

Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits.

Original language	English
Pages (from-to)	495
Number of pages	1
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	4
Issue number	4
DOIs	https://doi.org/10.1109/TVLSI.1996.544414
Publication status	Published - Dec 1996

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10.1109/TVLSI.1996.544414

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Tsui, C. Y., Monteiro, J., Pedram, M., Devadas, S., Despain, A. M., & Lin, B. (1996). Correction to “Power Estimation Methods for Sequential Logic Circuits” (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1995) 3(3) (404–416) (10.1109/92.406998)). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 4(4), 495. https://doi.org/10.1109/TVLSI.1996.544414

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title = "Correction to “Power Estimation Methods for Sequential Logic Circuits” (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1995) 3(3) (404–416) (10.1109/92.406998))",

abstract = "Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits.",

author = "Tsui, \{Chi Ying\} and Jos{\'e} Monteiro and Massoud Pedram and Srinivas Devadas and Despain, \{Alvin M.\} and Bill Lin",

year = "1996",

month = dec,

doi = "10.1109/TVLSI.1996.544414",

language = "English",

volume = "4",

pages = "495",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

Tsui, CY, Monteiro, J, Pedram, M, Devadas, S, Despain, AM & Lin, B 1996, 'Correction to “Power Estimation Methods for Sequential Logic Circuits” (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1995) 3(3) (404–416) (10.1109/92.406998))', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 4, pp. 495. https://doi.org/10.1109/TVLSI.1996.544414

Correction to “Power Estimation Methods for Sequential Logic Circuits” (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1995) 3(3) (404–416) (10.1109/92.406998)). / Tsui, Chi Ying; Monteiro, José; Pedram, Massoud et al.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 4, No. 4, 12.1996, p. 495.

Research output: Contribution to journal › Comment/debate

TY - JOUR

T1 - Correction to “Power Estimation Methods for Sequential Logic Circuits” (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1995) 3(3) (404–416) (10.1109/92.406998))

AU - Tsui, Chi Ying

AU - Monteiro, José

AU - Pedram, Massoud

AU - Devadas, Srinivas

AU - Despain, Alvin M.

AU - Lin, Bill

PY - 1996/12

Y1 - 1996/12

N2 - Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits.

AB - Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits.

UR - https://openalex.org/W2034283065

UR - https://www.scopus.com/pages/publications/85008014323

U2 - 10.1109/TVLSI.1996.544414

DO - 10.1109/TVLSI.1996.544414

M3 - Comment/debate

SN - 1063-8210

VL - 4

SP - 495

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 4

ER -

Correction to “Power Estimation Methods for Sequential Logic Circuits” (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1995) 3(3) (404–416) (10.1109/92.406998))

Abstract

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