Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

Talib Al-Ameri; Y. Wang; V. P. Georgiev; F. Adamu-Lema; X. Wang; A. Asenov

doi:10.1109/NMDC.2015.7439240

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

Talib Al-Ameri, Y. Wang, V. P. Georgiev, F. Adamu-Lema, X. Wang, A. Asenov

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

8 Citations (Scopus)

Abstract

In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrodinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.

Original language	English
Title of host publication	2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467393621
DOIs	https://doi.org/10.1109/NMDC.2015.7439240
Publication status	Published - 22 Mar 2016
Externally published	Yes
Event	10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 - Anchorage, United States Duration: 12 Sept 2015 → 16 Sept 2015

Publication series

Name	2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

Conference

Conference	10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
Country/Territory	United States
City	Anchorage
Period	12/09/15 → 16/09/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

CMOS
TCAD
electrostatics
nanowire transistors
performance
quantum effects

Access to Document

10.1109/NMDC.2015.7439240

Cite this

Al-Ameri, T., Wang, Y., Georgiev, V. P., Adamu-Lema, F., Wang, X., & Asenov, A. (2016). Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors. In 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 Article 7439240 (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NMDC.2015.7439240

Al-Ameri, Talib ; Wang, Y. ; Georgiev, V. P. et al. / Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors. 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015).

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title = "Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors",

abstract = "In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrodinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.",

keywords = "CMOS, TCAD, electrostatics, nanowire transistors, performance, quantum effects",

author = "Talib Al-Ameri and Y. Wang and Georgiev, \{V. P.\} and F. Adamu-Lema and X. Wang and A. Asenov",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 ; Conference date: 12-09-2015 Through 16-09-2015",

year = "2016",

month = mar,

day = "22",

doi = "10.1109/NMDC.2015.7439240",

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Al-Ameri, T, Wang, Y, Georgiev, VP, Adamu-Lema, F, Wang, X & Asenov, A 2016, Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors. in 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015., 7439240, 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015, Institute of Electrical and Electronics Engineers Inc., 10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015, Anchorage, United States, 12/09/15. https://doi.org/10.1109/NMDC.2015.7439240

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors. / Al-Ameri, Talib; Wang, Y.; Georgiev, V. P. et al.
2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7439240 (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

AU - Al-Ameri, Talib

AU - Wang, Y.

AU - Georgiev, V. P.

AU - Adamu-Lema, F.

AU - Wang, X.

AU - Asenov, A.

PY - 2016/3/22

Y1 - 2016/3/22

N2 - In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrodinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.

AB - In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrodinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.

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KW - TCAD

KW - electrostatics

KW - nanowire transistors

KW - performance

KW - quantum effects

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T3 - 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

BT - 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

Y2 - 12 September 2015 through 16 September 2015

ER -

Al-Ameri T, Wang Y, Georgiev VP, Adamu-Lema F, Wang X, Asenov A. Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors. In 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7439240. (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015). doi: 10.1109/NMDC.2015.7439240

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

Abstract

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Bibliographical note

Keywords

Access to Document

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