Demonstration of One Transistor-One Diode (1T1D) p-GaN/AlGaN/GaN Memory Cell

Youyi Yin; Teng Li; Junjie Yang; Jingjing Yu; Yunhong Lao; Hao Chang; Jialin Duan; Xiaosen Liu; Maojun Wang; Kechao Tang; Yimao Cai; Bo Shen; Jin Wei

doi:10.1109/LED.2025.3581752

Demonstration of One Transistor-One Diode (1T1D) p-GaN/AlGaN/GaN Memory Cell

Youyi Yin, Teng Li, Junjie Yang, Jingjing Yu, Yunhong Lao, Hao Chang, Jialin Duan, Xiaosen Liu, Maojun Wang, Kechao Tang, Yimao Cai, Bo Shen, Jin Wei^*

^*Corresponding author for this work

Research output: Contribution to journal › Journal Article › peer-review

Abstract

This letter demonstrates a one transistor - one diode p-GaN/AlGaN/GaN (1T1D) memory cell for potential applications in harsh-environment GaN integrated circuits. The 1T1D memory consists of a metal/insulator/ p-GaN gate HEMT (MIP-HEMT) and a p-GaN/AlGaN/GaN heterojunction diode (D1). The writing ‘0’ process (W0) is accomplished by the injection of holes from the p-GaN through the parasitic heterojunction diode within the transistor (D2), resulting in a storage of negative charges inside the p-GaN layer. The writing ‘1’ process (W1) involves the refill of holes into the p-GaN gate via D1. A large V_TH window (>5 V) is obtained, and the current margin (I₁–I₀) is ~30 mA/mm.

Original language	English
Pages (from-to)	1277-1280
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	46
Issue number	8
DOIs	https://doi.org/10.1109/LED.2025.3581752
Publication status	Published - 2025
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 1980-2012 IEEE.

Keywords

GaN 1T1D memory
V shift
current margin
hole storage in p-GaN
p-GaN gate HEMT platform

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title = "Demonstration of One Transistor-One Diode (1T1D) p-GaN/AlGaN/GaN Memory Cell",

abstract = "This letter demonstrates a one transistor - one diode p-GaN/AlGaN/GaN (1T1D) memory cell for potential applications in harsh-environment GaN integrated circuits. The 1T1D memory consists of a metal/insulator/ p-GaN gate HEMT (MIP-HEMT) and a p-GaN/AlGaN/GaN heterojunction diode (D1). The writing {\textquoteleft}0{\textquoteright} process (W0) is accomplished by the injection of holes from the p-GaN through the parasitic heterojunction diode within the transistor (D2), resulting in a storage of negative charges inside the p-GaN layer. The writing {\textquoteleft}1{\textquoteright} process (W1) involves the refill of holes into the p-GaN gate via D1. A large VTH window (>5 V) is obtained, and the current margin (I1–I0) is \textasciitilde{}30 mA/mm.",

keywords = "GaN 1T1D memory, V shift, current margin, hole storage in p-GaN, p-GaN gate HEMT platform",

author = "Youyi Yin and Teng Li and Junjie Yang and Jingjing Yu and Yunhong Lao and Hao Chang and Jialin Duan and Xiaosen Liu and Maojun Wang and Kechao Tang and Yimao Cai and Bo Shen and Jin Wei",

note = "Publisher Copyright: {\textcopyright} 1980-2012 IEEE.",

year = "2025",

doi = "10.1109/LED.2025.3581752",

language = "English",

volume = "46",

pages = "1277--1280",

journal = "IEEE Electron Device Letters",

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T1 - Demonstration of One Transistor-One Diode (1T1D) p-GaN/AlGaN/GaN Memory Cell

AU - Yin, Youyi

AU - Li, Teng

AU - Yang, Junjie

AU - Yu, Jingjing

AU - Lao, Yunhong

AU - Chang, Hao

AU - Duan, Jialin

AU - Liu, Xiaosen

AU - Wang, Maojun

AU - Tang, Kechao

AU - Cai, Yimao

AU - Shen, Bo

AU - Wei, Jin

PY - 2025

Y1 - 2025

N2 - This letter demonstrates a one transistor - one diode p-GaN/AlGaN/GaN (1T1D) memory cell for potential applications in harsh-environment GaN integrated circuits. The 1T1D memory consists of a metal/insulator/ p-GaN gate HEMT (MIP-HEMT) and a p-GaN/AlGaN/GaN heterojunction diode (D1). The writing ‘0’ process (W0) is accomplished by the injection of holes from the p-GaN through the parasitic heterojunction diode within the transistor (D2), resulting in a storage of negative charges inside the p-GaN layer. The writing ‘1’ process (W1) involves the refill of holes into the p-GaN gate via D1. A large VTH window (>5 V) is obtained, and the current margin (I1–I0) is ~30 mA/mm.

AB - This letter demonstrates a one transistor - one diode p-GaN/AlGaN/GaN (1T1D) memory cell for potential applications in harsh-environment GaN integrated circuits. The 1T1D memory consists of a metal/insulator/ p-GaN gate HEMT (MIP-HEMT) and a p-GaN/AlGaN/GaN heterojunction diode (D1). The writing ‘0’ process (W0) is accomplished by the injection of holes from the p-GaN through the parasitic heterojunction diode within the transistor (D2), resulting in a storage of negative charges inside the p-GaN layer. The writing ‘1’ process (W1) involves the refill of holes into the p-GaN gate via D1. A large VTH window (>5 V) is obtained, and the current margin (I1–I0) is ~30 mA/mm.

KW - GaN 1T1D memory

KW - V shift

KW - current margin

KW - hole storage in p-GaN

KW - p-GaN gate HEMT platform

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DO - 10.1109/LED.2025.3581752

M3 - Journal Article

AN - SCOPUS:105008949610

SN - 0741-3106

VL - 46

SP - 1277

EP - 1280

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 8

ER -

Demonstration of One Transistor-One Diode (1T1D) p-GaN/AlGaN/GaN Memory Cell

Abstract

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Keywords

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