Abstract
An exponentially scaling C-2C switched-capacitor (SC) ladder is proposed for millimeter-wave digitally controlled oscillators (DCOs) to achieve high-frequency resolution with small chip area. The 65-nm-CMOS DCO prototype measures a frequency resolution of 4 Hz over a frequency range of 14.2%, from 54.79 to 63.16 GHz, with a phase noise at 1-MHz frequency offset of -90.7 to -94.1 dBc/Hz while consuming 18 mW, corresponding to an FOMT from -176.6 to -180 dB. The DCO occupies a core area of 0.10 mm2, with only 0.012 mm2 for the C-2C SC ladder.
| Original language | English |
|---|---|
| Article number | 7862162 |
| Pages (from-to) | 1299-1307 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Volume | 64 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - Jun 2017 |
Bibliographical note
Publisher Copyright:© 2017 IEEE.
Keywords
- All-digital phase-locked loop (ADPLL)
- C-2C
- digitally controlled oscillator (DCO)
- ditheringless
- exponentially scaling
- frequency resolution
- millimeter-wave (mmW)
- oscillator
- quantization noise
- switched capacitor (SC)
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