Design for Delay Fault Testability

This chapter presents design techniques to improve the delay fault testability. Since in many designs, the coverage for path delay faults is un-acceptably low, most of the research in this area has concentrated on improving the path delay fault testability. Path delay fault testability can be defined with respect to several factors: the number of faults to be tested, the number of tests that need to be applied to test all path delay faults, the number of faults that can be guaranteed to be detected independent of delays outside the target path, etc. This chapter describes design for testability techniques such as test point insertion and use of partial scan as well as techniques for resynthesizing the circuit such that its path delay fault testability is improved.