Design of a 2.2-mW 24-Mb/s CMOS VLC Receiver SoC with Ambient Light Rejection and Post-Equalization for Li-Fi Applications

This paper presents an energy-efficient visible light communication (VLC) receiver system-on-a-chip (SoC) that employs ambient light rejection (ALR) and post-equalization techniques for emerging light fidelity (Li-Fi) applications using ordinary phosphorescent white light-emitting diodes (LEDs). A current-reuse transimpedance amplifier is proposed for energy-efficient applications. An ALR unit is implemented to eliminate the potential DC interference under strong ambient light. A two-stage continuous-time linear equalizer is utilized to compensate for the limited bandwidth of white LEDs, which is below 3 MHz. Implemented in a 0.18 μm CMOS process, the receiver occupies an area of 0.7 × 0.4 mm² and consumes 2.2 mW of power at 24 Mb/s from a 1.8 V power supply. An IEEE 802.15.7 PHY-II compliant Li-Fi link that employs the proposed receiver SoC and a custom transmitter SoC is demonstrated based on 1-W phosphorescent white LEDs without using blue filtering, achieving a bit error rate of 1 × 10^-9 for data rates up to 24 Mb/s over 1.6 m distance, and 22 Mb/s over 2.7 m distance, with on-off keying modulation and 2¹¹-1 pseudorandom binary sequence (PRBS-11) optical inputs. The receiver SoC achieves a bit efficiency six times better than that of the prior art using off-the-shelf discrete components, and can tolerate an ambient light level of 3500 lx. A figure of merit accommodating the most important system parameters is also proposed for a comprehensive comparison of different VLC systems.